MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 381

Manufacturer Part Number

BOARD DEVELOPMENT SYSTEM 8544

Manufacturer

Freescale Semiconductor

PowerQUICC III™r

Processor To Be Evaluated

Data Bus Width

Interface Type

Ethernet, I2C

Operating Supply Voltage

- 0.3 V to + 1.1 V

Leaded Process Compatible

Peak Reflow Compatible (260 C)

Rohs Compliant

For Use With/related Products

For Use With

PPC8544EVTANG - EVAL MPC8544 783FCPBGA

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Freescale Semiconductor

If running with many devices, zero-delay PLL clock buffers, JEDEC-JESD82 standard, should be

used. These buffers were designed for DDR applications.

A 72 bit x 64 Mbytes DDR bank has 9-byte-wide DDR chips, resulting in 18 DDR chips in a

two-bank system. In this case, each MCK/MCK signal pair should drive exactly three devices.

PCB traces for DDR clock signals should be short, all on the same layer, and of equal length and

DDR SDRAM manufacturers provide detailed information on PCB layout and termination issues.

Clock Distribution

MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1

Figure 9-40. DDR SDRAM 4-Beat Burst Write Timing—ACTTORW = 4

DDR Memory Controller