MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 736

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
15.3
The eTSEC’s primary operational modes are the following:
15-4
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— Retransmission following a collision
— Support for CRC generation and verification of inbound/outbound packets
— Programmable Ethernet preamble insertion and extraction of up to 7 bytes
MAC address recognition:
— Exact match on primary and virtual 48-bit unicast addresses
— Broadcast address (accept/reject)
— Hash table match on up to 256 unicast/multicast or 512 multicast-only addresses
— Promiscuous mode
Remote network monitoring (RMON) statistics support
— 32-bit byte counters
— Carry/Overflow of counter interrupts
Backward compatibility with MPC8540E/MPC8560E (PowerQUICC III) TSEC
— PowerQUICC III buffer descriptor (BD) format and rings supported
— Common register memory map, with specific exceptions:
— Reset state of eTSEC defaults to common PowerQUICC III TSEC subset
— TSEC_ID register permits TSEC versus enhanced TSEC differentiation
Ethernet and FIFO operation
The ECNTRL register’s FIFO mode enable bit (ECNTRL[FIFM]) allows bypass of the Ethernet
MAC and enables I/O through the FIFO interface sharing the normal GMII signals. Each eTSEC
supports an 8-bit FIFO interface independently. If configured in FIFO mode, the FIFOCFG register
determines operation. In FIFO mode data is transferred synchronously with respect to the external
data clock, whose maximum is defined by a ratio of 4.2:1 (platform:TxClk) in GMII mode and a
ratio of 3.2:1 (platform:TxClk) in encoded mode.
Full- and half-duplex operation
This is determined by the MACCFG2 register’s full-duplex bit (MACCFG2[Full Duplex]).
Full-duplex mode is intended for use on point-to-point links between switches or end node to
Modes of Operation
– Per-frame VLAN control word or default VLAN for each eTSEC
– Extracted VLAN control word passed to software separately
– Programmable VLAN tag to support metropolitan bridging
– VRRP and HSRP support for seamless router fail-over
– In addition to primary station address, up to fifteen additional exact-match MAC addresses
– Out-of-sequence transmit BD not supported
– Internal DMA BD pointers and data counts not visible
– MINFLR register not supported
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
supported
Freescale Semiconductor