MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 182

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reset, Clocking, and Initialization
4.4.4.2
Clocks for these high speed interfaces on the MPC8544E are derived from a PLL in the SerDes block. This
PLL is driven by a reference clock (SD_REF_CLK/SD_REF_CLK) whose input frequency is a function
of the protocol and bit rate being used as shown in
4.4.4.2.1
Section 4.4.3.6, “I/O Port
that the CCB clock frequency must be considered for proper operation of such interfaces as described
below.
4-24
cfg_core_pll[0:2]
cfg_sys_pll[0:3]
PCI_CLK
SYSCLK
PCI Express and SGMII Clocks
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Minimum Frequency Requirements
PCI Express
Interfaces
SGMII
MPC8544E
4
3
Selection,” describes various high-speed interface configuration options. Note
Figure 4-6. Clock Subsystem Block Diagram
Table 4-32. High Speed Interface Clocking
Device PLL
e500 Core
PCI
1.25 Gbps
2.5 Gbps
Bit Rate
CCB_clk
Core PLL
CCB_clk to Rest
of the Device
Table
100 MHz (Spread Spectrum supported)
÷
÷
n
4-32.
2
Reference Clock Frequency
DDR
PLL
core_clk
100 MHz
6
6
MCK[0:5]
MCK[0:5]
LSYNC_IN
LSYNC_OUT
LCLK0
LCLK1
LCLK2
Freescale Semiconductor
DDR
Controller
LBC