MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 890

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
15.6.4.1
Frame control blocks (FCBs) are 8-byte blocks of TOE control and/or status data that are passed between
software (driver and TCP/IP stack) and each eTSEC. A FCB always precedes the frame it applies to, and
is present only when TOE functions are being used. As
points to the initial data buffer and the FCB. The initial data buffer must be at least 8 bytes long to contain
the FCB without breaking it. Custom or received Ethernet preamble sequences also follow the FCB if
preambles are visible.
For TxBD rings, FCBs are assumed present when the TxBD[TOE/UN] bit is set by user software. The
eTSEC ignores the TxBD[TOE/UN] bit in all BDs other than those pointing to initial data buffers,
therefore FCBs must not be inserted in second and subsequent data buffers. Since TxBD[TOE/UN] can be
set under software discretion, TOE acceleration for transmit may be applied on a frame-by-frame basis.
In the case of RxBD rings, FCBs are inserted by the eTSEC whenever RCTRL[PRSDEP] is set to a
non-zero value. Only one FCB is inserted per frame, in the buffer pointed to by the RxBD with bit F set.
TOE acceleration for receive is enabled for all frames in this case.
15.6.4.2
TOE functions for transmit are defined by the contents of the Tx FCB.
definition for the Tx FCB.
15-158
Offset + 0
Offset + 2
Offset + 4
Offset + 6
Frame Control Blocks
Transmit Path Off-Load
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
VLN
BD
0
Figure 15-129. Location of Frame Control Blocks for TOE Parameters
IP
1
FCB
L3OS
L2 HDR
IP6
(last)
2
BD
Figure 15-130. Transmit Frame Control Block
TUP UDP CIP CTU NPH
3
L4OS
L4OS
L3 HDR
Frame data, first buffer
4
(first)
BD
5
L4 HDR
6
(last)
BD
7
VLCTL
Figure 15-129
PHCS
8
BD
9
Frame data, second buffer
BD ring
shows, the first BD of each frame
10
Figure 15-130
11
L3OS
12
Freescale Semiconductor
describes the
13
14
15