MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 1325
![BOARD DEVELOPMENT SYSTEM 8544](/photos/37/58/375876/mpc8544e_sml.jpg)
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
- Current page: 1325 of 1340
- Download datasheet (12Mb)
Interrupts
IRQ[0:11] (interrupt request 0–11) signals, 10-8
Freescale Semiconductor
reset of PIC, 10-20, 10-53
reset processor from software, 10-21
signals summary, 10-7
simultaneous interrupts, priorities, 10-50
sources of interrupts, 10-5
spurious vector generation, 10-23, 10-51
vendor identification, 10-21
DDR, 9-37
DMA, 16-10–16-13, 16-15, 16-20, 16-24, 16-33
DUART
e500 core
ECM interrupt register (ECM error enable
eTSEC, 15-152–15-155
I
IRQ[9:11] signal select, 19-13, 19-35
LBC interrupt register, 14-26
PCI/PCI-X error enable register, 17-26
performance monitor (PIC), 20-20
power management and interrupts (global utilities), 19-33
security engine (SEC), 12-103–12-104, 12-108
see also Interrupt controller (PIC)
2
C interface
message registers, 10-34–10-36
non-accessible registers
per-CPU registers, 10-44–10-48
performance monitor mask registers, 10-32–10-34
summary registers, 10-28–10-32
see also Signals, PIC
internal (to PIC) interrupt destinations, 10-29, 10-30,
internal (to PIC) interrupt sources, 10-6
interrupt control logic, 13-23
interrupt enable and control registers, 13-9–13-11
registers, 6-17–6-22
interrupt registers, 15-24–15-30
calling address match condition, 11-6
flowchart for interrupt service routine, 11-24
interrupt after transfer, 11-22
interrupt enable bit (I2CCR[MIEN]), 11-8
interrupt on START, 11-22
interrupt pending status bit (I2CSR[MIF]), 11-10
interrupt-driven byte-to-byte transfers, 11-2
read of last byte, 11-23
slave mode interrupt service routine guidelines, 11-23
registers, 12-110–12-112
in-service register (ISR), 10-50
interrupt pending register (IPR), 10-48
interrupt request register (IRR), 10-48
register—EEER), 8-7
for slave transmitter routine, 11-24
loss of arbitration, 11-24
10-31, 10-32
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
IRQ[9:11] signal select
IRQ_OUT (interrupt request out) signal, 10-8, 10-28
IVORn (interrupt vector offset registers), see e500 core,
IVPR (interrupt vector prefix register), see e500 core,
J
JEDEC SDRAM commands (LBC), 14-49
JTAG test access port
L
L1CFG0–1 (L1 cache configuration registers 0–1), see e500
L1CSR0–1 (L1 cache status and control registers 0–1), see
L2 cache/SRAM
LA[27:31] (LBC non-multiplexed address) signals, 14-7
LAD[0:31] (LBC multiplexed address/data) signals, 14-7
global utilities, 19-13
signals summary, 21-5
allocation of lines, 7-32
block diagram, 7-1
coherency rules, 7-28
error handling registers, 7-17
error injection, 7-18
external writes, see stashing
flash clearing, instruction and data locks, 7-31
locking
memory map/register definition, 7-8
memory-mapped SRAM
memory-mapped windows, 2-4
operation, 7-33
overview, 7-1
performance monitor events, 20-26
PLRU bit update considerations, 7-32
register descriptions, 7-10–7-25
replacement policy, 7-31
SRAM features, 7-2
stashing, 7-25
state transitions, 7-35
timing, 7-27
registers
registers
see also Signals, JTAG, 21-5
core, registers
e500 core, registers
clearing locks on selected lines, 7-30
entire, 7-29
programmed memory ranges, 7-30
selected lines, 7-30
with stale data, 7-31
coherency rules, 7-29
due to core-initiated transactions, 7-35
due to system-initiated transactions, 7-38
Index-9
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