MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 516
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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- Download datasheet (12Mb)
Security Engine (SEC) 2.1
12.4.2.5
This status register, shown in
signals. The DEU status register is read-only. Writing to this location results in an address error being
reflected in the DEU interrupt status register.
Table 12-18
12-36
Bits Names
Address DEU 0x3_2028
40–47
48–55
56–57
59–60
62
63
0–39
Bits
58
61
Reset
W
R
SR
MI
Name
HALT Halt. Indicates that the DEU has halted due to an error.
0
OFL
IFL
—
—
—
IE
describes the DEU status register bit settings.
Module initialization is nearly the same as software reset, except that the interrupt control register remains
unchanged. this module initialization includes execution of an initialization routine, completion of which is
indicated by the RESET_DONE bit in the DEU status register
0 Don’t reset
1 Reset most of DEU
Software reset is functionally equivalent to hardware reset (the RESET signal), but only for DEU. All registers
and internal state are returned to their defined reset state. Upon negation of SW_RESET, the DEU enters a
routine to perform proper initialization of the parameter memories. The RESET_DONE bit in the DEU status
register indicates when this initialization routine is complete
0 Don’t reset
1 Full DEU reset
DEU Status Register (DEUSR)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved
The number of dwords currently in the output FIFO
The number of dwords currently in the input FIFO
Reserved
0 DEU not halted
1 DEU halted
Note: Because the error causing the DEU to stop operating may be masked before reaching the interrupt
Reserved
Interrupt error. This status bit reflects the state of the ERROR interrupt signal, as sampled by the controller
interrupt status register
0 DEU is not signaling error
1 DEU is signaling error
Table 12-17. DEU Reset Control Register Field Descriptions (continued)
status register, the DEU interrupt status register is used to provide a second source of information
regarding errors preventing normal operation.
Table 12-18. DEU Status Register Field Descriptions
Figure
—
(Section 12.6.5.3, “Interrupt Status Register
Figure 12-17. DEU Status Register
12-17, contains 6 fields which reflect the state of DEU internal
All zeros
39 40
Description
Description
—
OFL
47 48
(ISR)”).
IFL
55 56 57
—
Freescale Semiconductor
HALT
58
Access: Read-only
59 60 61 62
—
IE ID RD
63
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