MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 258
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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- Download datasheet (12Mb)
Core Register Summary
6-40
34–35
42–43
44–45
46–47
Bits
32
33
36
37
38
39
40
41
Name
TRAP Trap debug event enable
DAC1 Data address compare 1 debug event enable
DAC2 Data address compare 2 debug event enable
ICMP
IRPT
IAC1
IAC2
RST
BRT
IDM
—
—
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved, should be cleared.
Internal debug mode
0 Debug interrupts are disabled. No debug interrupts are taken and debug events are not logged.
1 If MSR[DE] = 1, the occurrence of a debug event or the recording of an earlier debug event in the DBSR
Programming note: Software must clear debug event status in the DBSR in the debug interrupt handler
when a debug interrupt is taken before re-enabling interrupts through MSR[DE]. Otherwise, redundant debug
interrupts are taken for the same debug event.
Reset. The e500 implements these bits as follows:
0 x Default (No action)
1 x Causes a hard reset if MSR[DE] and DBCR0[IDM] are set. Always cleared on subsequent cycle. This
Instruction completion debug event enable
0 ICMP debug events are disabled
1 ICMP debug events are enabled
Note: Instruction completion does not cause an ICMP debug event if MSR[DE] = 0.
Branch taken debug event enable
0 BRT debug events are disabled
1 BRT debug events are enabled
Note: Taken branches do not cause a BRT debug event if MSR[DE] = 0.
Interrupt taken debug event enable. This bit affects only noncritical interrupts.
0 IRPT debug events are disabled
1 IRPT debug events are enabled
0 TRAP debug events cannot occur
1 TRAP debug events can occur
Instruction address compare 1 debug event enable
0 IAC1 debug events cannot occur
1 IAC1 debug events can occur
Instruction address compare 2 debug event enable
0 IAC2 debug events cannot occur
1 IAC2 debug events can occur
Reserved, should be cleared.
00 DAC1 debug events cannot occur
01 DAC1 debug events can occur only if a store-type data storage access
10 DAC1 debug events can occur only if a load-type data storage access
11 DAC1 debug events can occur on any data storage access
00 DAC2 debug events cannot occur
01 DAC2 debug events can occur only if a store-type data storage access
10 DAC2 debug events can occur only if a load-type data storage access
11 DAC2 debug events can occur on any data storage access
when MSR[DE] = 0 or DBCR0[IDM] = 0 causes a debug interrupt.
causes a hard reset to the core only.
Table 6-35. DBCR0 Field Descriptions
Description
Freescale Semiconductor
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