MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 375
![BOARD DEVELOPMENT SYSTEM 8544](/photos/37/58/375876/mpc8544e_sml.jpg)
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
- Current page: 375 of 1340
- Download datasheet (12Mb)
14 x 10
14 x 10
13 x 10
13 x 10
Chip select interleaving is supported for the memory controller, and is programmed in
DDR_SDRAM_CFG[BA_INTLV_CTL]. Interleaving is supported between chip selects 0 and 1 or chip
selects 2 and 3. In addition, interleaving between all four chip selects can be enabled. When interleaving
is enabled, the chip selects being interleaved must use the same size of memory. If two chip selects are
interleaved, then 1 extra bit in the address decode is used for the interleaving to determine which chip
select to access. If four chip selects are interleaved, then two extra bits are required in the address decode.
Table 9-44
Table 9-45
Freescale Semiconductor
10 x 2
9 x 2
x 3
x 2
x 3
x 2
13 x
13 x
Row
Col
Row
Table 9-43. DDR2 Address Multiplexing for 32-Bit Data Bus with Interleaving Disabled (continued)
Col
x
x
MRAS
MCAS
MRAS
MCAS
MRAS
MCAS
MRAS
MCAS
MRAS
MCAS
MRAS
MCAS
MBA
MBA
MBA
MBA
MBA
MBA
Table 9-44. Example of Address Multiplexing for 64-Bit Data Bus Interleaving Between
illustrates examples of address decode when interleaving between two chip selects, and
shows examples of address decode when interleaving between four chip selects.
msb
msb
4
4
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
13 12 11 10 9 8 7 6 5 4 3 2 1 0
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34–35
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
13 12 11 10 9 8 7 6 5 4 3 2 1
12 11 10 9
12 11 10 9
12 11 10 9
12 11 10 9
8
7
8
6
7
8
5
6
7
8
4
5
Address from Core Master
6
7
Address from Core Master
3
4
Two Banks
5
6
2
3
4
5
1
2
3
4
0
1
SEL
SEL
2
3
CS
CS
0
0
1
2
SEL
SEL
CS
CS
20 21 22 23 24 25 26 27 28 29 30 31 32 33–35
0
1
2
2
1
0
1 0
1 0
1
1
0
1
0
0
9
0
9 8 7 6 5 4 3 2 1 0
9 8 7 6 5 4 3 2 1 0
9
9
8
8
8
8
7
7
7
7
6
6
6
6
5
5
5
5
4
4
DDR Memory Controller
4
4
3
3
3
3
2
2
2
2
1
1
1
1
0
0
0
0
lsb
9-51
lsb
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