MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 32

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Paragraph
Number
15.6.5.1.8
15.6.5.2
15.6.5.2.1
15.6.5.2.2
15.6.6
15.6.6.1
15.6.6.2
15.6.6.2.1
15.6.6.2.2
15.6.7
15.6.7.1
15.6.7.2
15.6.7.3
15.7
15.7.1
15.7.1.1
15.7.1.2
15.7.1.3
15.7.1.4
15.7.1.5
15.7.1.6
15.7.1.7
15.7.1.8
16.1
16.1.1
16.1.2
16.1.3
16.1.4
16.2
16.2.1
16.2.2
16.3
16.3.1
16.3.1.1
16.3.1.2
16.3.1.3
xxxii
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Initialization/Application Information ....................................................................... 15-179
Introduction.................................................................................................................... 16-1
External Signal Description ........................................................................................... 16-5
Memory Map/Register Definition ................................................................................. 16-6
Lossless Flow Control ........................................................................................... 15-170
Buffer Descriptors.................................................................................................. 15-173
Interface Mode Configuration ............................................................................... 15-179
Block Diagram........................................................................................................... 16-1
Overview.................................................................................................................... 16-2
Features...................................................................................................................... 16-2
Modes of Operation ................................................................................................... 16-2
Signal Overview ........................................................................................................ 16-5
Detailed Signal Descriptions ..................................................................................... 16-6
DMA Register Descriptions....................................................................................... 16-9
Transmission Scheduling................................................................................... 15-168
Back Pressure Determination via Free Buffers.................................................. 15-170
Data Buffer Descriptors ..................................................................................... 15-173
Transmit Data Buffer Descriptors (TxBD) ........................................................ 15-174
Receive Buffer Descriptors (RxBD).................................................................. 15-177
MII Interface Mode............................................................................................ 15-180
GMII Interface Mode......................................................................................... 15-184
TBI Interface Mode ........................................................................................... 15-188
RGMII Interface Mode ...................................................................................... 15-192
RMII Interface Mode......................................................................................... 15-196
RTBI Interface Mode......................................................................................... 15-200
8-Bit FIFO Mode ............................................................................................... 15-204
SGMII Interface Support ................................................................................... 15-206
Mode Registers (MRn) ........................................................................................ 16-10
Status Registers (SRn) ......................................................................................... 16-12
Current Link Descriptor Address Registers (CLNDARn and
Software Use of Hardware-Initiated Back Pressure .......................................... 15-172
Filer Example—TCP and UDP Port Filing .................................................. 15-167
Priority-Based Queuing (PBQ)...................................................................... 15-168
Modified Weighted Round-Robin Queuing (MWRR) .................................. 15-169
Initialization................................................................................................... 15-172
Operation ....................................................................................................... 15-172
ECLNDARn) ................................................................................................... 16-13
DMA Controller
Contents
Chapter 16
Title
Freescale Semiconductor
Number
Page