MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 59
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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- Download datasheet (12Mb)
Figure
Number
15-122
15-123
15-124
15-125
15-126
15-127
15-128
15-129
15-130
15-131
15-132
15-133
15-134
15-135
15-136
15-137
15-138
16-1
16-2
16-3
16-4
16-5
16-6
16-7
16-8
16-9
16-10
16-11
16-12
16-13
16-14
16-15
16-16
16-17
16-18
16-19
16-20
16-21
16-22
16-23
16-24
Freescale Semiconductor
eTSEC-FIFO (8-Bit) Connection...................................................................................... 15-139
8-Bit GMII-Style Packet FIFO Timing ............................................................................. 15-139
8-Bit Encoded Packet FIFO Timing ................................................................................. 15-140
Definition of Custom Preamble Sequence ........................................................................ 15-146
Definition of Received Preamble Sequence...................................................................... 15-147
Ethernet Address Recognition Flowchart ......................................................................... 15-148
Sample C Code for Computing eTSEC Hash Table Indices............................................. 15-150
Location of Frame Control Blocks for TOE Parameters .................................................. 15-158
Transmit Frame Control Block ......................................................................................... 15-158
Receive Frame Control Block........................................................................................... 15-160
Structure of the Receive Queue Filer Table ...................................................................... 15-163
Example of eTSEC Memory Structure for BDs ............................................................... 15-173
Buffer Descriptor Ring...................................................................................................... 15-174
Transmit Buffer Descriptor ............................................................................................... 15-174
Mapping of TxBDs to a C Data Structure......................................................................... 15-175
Receive Buffer Descriptor................................................................................................. 15-177
Mapping of RxBDs to a C Data Structure ........................................................................ 15-178
DMA Block Diagram............................................................................................................ 16-1
DMA Operational Flow Chart .............................................................................................. 16-4
DMA Signal Summary.......................................................................................................... 16-5
DMA Mode Registers (MRn) ............................................................................................. 16-10
Status Registers (SRn)......................................................................................................... 16-12
Basic Chaining Mode Flow Chart....................................................................................... 16-14
Extended Current Link Descriptor Address Registers (ECLNDARn) ............................... 16-14
Current Link Descriptor Address Registers (CLNDARn) .................................................. 16-15
Source Attributes Registers (SATRn) ................................................................................. 16-16
Source Address Registers (SARn) ...................................................................................... 16-17
Destination Attributes Registers (DATRn) ......................................................................... 16-17
Destination Address Registers (DARn) .............................................................................. 16-19
Byte Count Registers (BCRn)............................................................................................. 16-19
Next Link Descriptor Address Registers (NLNDARn) ...................................................... 16-20
Extended Next Link Descriptor Address Registers (ENLNDARn).................................... 16-20
Extended Current List Descriptor Address Registers (ECLSDARn) ................................. 16-21
Current List Descriptor Address Registers (CLSDARn) .................................................... 16-21
Extended Next List Descriptor Address Registers (ENLSDARn)...................................... 16-22
Next List Descriptor Address Registers (NLSDARn) ........................................................ 16-22
Source Stride Registers (SSRn) .......................................................................................... 16-23
Destination Stride Registers (DSRn) .................................................................................. 16-23
DMA General Status Register (DGSR) .............................................................................. 16-24
External Control Interface Timing ...................................................................................... 16-31
Stride Size and Stride Distance ........................................................................................... 16-33
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Figures
Title
Number
Page
lix
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