MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 238

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Core Register Summary
6.7.2
6.7.2.1
6.7.2.2
6-20
Reset
Reset
44–45
47–55
57–63
SPR 570
SPR 571
Bits
41
42
43
46
56
W
W
R
R
32
32
Name
SPE
DLK
ILK
BO
—
—
—
—
Additional Interrupt Registers
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Machine Check Save/Restore Register 0 (MCSRR0)
Machine Check Save/Restore Register 1 (MCSRR1)
Reserved, should be cleared.
Cache locking. Settings are implementation-dependent.
0 Default
1 On the e500, DLK is set when a DSI occurs because dcbtls, dcbtstls, or dcblc is
Set when a DSI occurs because icbtl or icblc is executed in user mode
(MSR[PR] = 1) and MSR[UCLE] = 0
Reserved, should be cleared.
Byte-ordering exception
Reserved, should be cleared.
SPE exception bit (e500-specific)
0 Default
1 Any exception caused by an SPE or SPFP instruction
Reserved, should be cleared.
executed in user mode while MSR[UCLE] = 0.
Figure 6-23. Machine Check Save/Restore Register 0 (MCSRR0)
Figure 6-24. Machine Check Save/Restore Register 1 (MCSRR1)
Table 6-12. ESR Field Descriptions (continued)
Next instruction address
MSR state information
Syndrome
All zeros
All zeros
Access: Supervisor read/write
Access: Supervisor read/write
Freescale Semiconductor
—
Data storage
Data storage
instruction storage
—
SPE unavailable
—
Data storage,
Interrupt Types
63
63