MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 343
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
- Current page: 343 of 1340
- Download datasheet (12Mb)
10–12
13–15
16–18
Table 9-11
Freescale Semiconductor
Bits
1–3
4–8
0
9
RD_TO_PRE
ADD_LAT
WR_LAT
describes the TIMING_CFG_2 fields.
Name
CPO
—
—
—
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
1
Reserved
Additive latency. The additive latency must be set to a value less than TIMING_CFG_1[ACTTORW].
(DDR2-specific)
000 0 clocks
001 1 clock
010 2 clocks
011 3 clocks
100 4 clocks
101 5 clocks
110 Reserved
111 Reserved
MCAS-to-preamble override. Defines the number of DRAM cycles between when a read is issued
and when the corresponding DQS preamble is valid for the memory controller. For these decodings,
“READ_LAT” is equal to the CAS latency plus the additive latency.
00000 READ_LAT + 1
00001 Reserved
00010 READ_LAT
00011 READ_LAT + 1/4
00100 READ_LAT + 1/2
00101 READ_LAT + 3/4
00110 READ_LAT + 1
00111 READ_LAT + 5/4
01000 READ_LAT + 3/2
01001 READ_LAT + 7/4
01010 READ_LAT + 2
01011 READ_LAT + 9/4
Reserved
Write latency. Note that the total write latency for DDR2 is equal to WR_LAT + ADD_LAT; the write
latency for DDR1 is 1.
000 Reserved
001 1 clock
010 2 clocks
011 3 clocks
100 4 clocks
101 5 clocks
110 6 clocks
111 7 clocks
Reserved
Read to precharge (t
ADD_LAT + t
to 010; for DDR1 with burst length of 8, must be set to 100.
000 Reserved
001 1 cycle
010 2 cycles
011 3 cycles
Table 9-11. TIMING_CFG_2 Field Descriptions
RTP
cycles between read and precharge. For DDR1 with burst length of 4, must be set
RTP
). For DDR2, with a non-zero ADD_LAT value, takes a minimum of
01100 READ_LAT + 5/2
01101 READ_LAT + 11/4
01110 READ_LAT + 3
01111 READ_LAT + 13/4
10000 READ_LAT + 7/2
10001 READ_LAT + 15/4
10010 READ_LAT + 4
10011 READ_LAT + 17/4
10100 READ_LAT + 9/2
10101 READ_LAT + 19/4
10110–11111 Reserved
100 4 cycles
101–111 Reserved
Description
DDR Memory Controller
9-19
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