MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 824

Manufacturer Part Number

BOARD DEVELOPMENT SYSTEM 8544

Manufacturer

Freescale Semiconductor

PowerQUICC III™r

Processor To Be Evaluated

Data Bus Width

Interface Type

Ethernet, I2C

Operating Supply Voltage

- 0.3 V to + 1.1 V

Leaded Process Compatible

Peak Reflow Compatible (260 C)

Rohs Compliant

For Use With/related Products

For Use With

PPC8544EVTANG - EVAL MPC8544 783FCPBGA

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers

15.5.3.6.24 Receive Dropped Packet Counter (RDRP)

Figure 15-75

15.5.3.6.25 Transmit Byte Counter (TBYT)

Figure 15-76

Offset eTSEC1:0x2_46DC; eTSEC3:0x2_56DC

Offset eTSEC1:0x2_46E0; eTSEC3:0x2_56E0

describes the fields of the RDRP register.

describes the fields of the TBYT register.

describes the definition for the RDRP register.

describes the definition for the TBYT register.

MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1

frames that were involved with collisions. This count does not include preamble/SFD or jam bytes.

Note that the value of TBYT may be greater than the actual number of bytes transmitted if the frame is

truncated because it exceeds MAXFRM.

Transmit byte counter. Increments by the number of bytes that were put on the wire including fragments of

Figure 15-75. Receive Dropped Packet Counter Register Definition

are later dropped due to lack of system resources.

Receive dropped packets counter. Increments for frames received which are streamed to system but

Figure 15-76. Transmit Byte Counter Register Definition

Table 15-78. RDRP Field Descriptions

Table 15-79. TBYT Field Descriptions

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