MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 420

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Programmable Interrupt Controller
Table 10-12
10.3.1.7
The interprocessor interrupt (IPI) vector/priority registers contain the interrupt vector and priority fields
for the four interprocessor interrupt channels as shown in
register per channel. The VECTOR and PRIORITY values should not be changed while IPIVPRn[A] is
set.
Table 10-13
10-22
12–15 PRIORITY Priority. Specifies the interrupt priority. The lowest priority is 0 and the highest priority is 15. A priority level of
16–31 VECTOR Vector. The vector value in this field is returned when the interrupt acknowledge (IACK) register is read and
2–11
Offset 0x4_10A0, 0x4_10B0, 0x4_10C0, 0x4_10D0
Reset
Bits
0–30
Bits
0
1
31
W
R
MSK
Name
1
0
Name
MSK
—
P0
A
—
A
1
0
describes the PIR fields.
describes the IPIVPRn fields.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
IPI Vector/Priority Registers (IPIVPR n )
Reserved
Processor 0 core reset. Setting this bit causes the PIC unit to assert the core_reset signal to processor 0 (the
e500 core).
0
2
Mask. Mask interrupts from this source. Always set following reset.
0 An interrupt request is generated if the corresponding IPR bit is set.
1 Further interrupts from this source are disabled.
Activity. Indicates an interrupt has been reported or is in-service. Note that this field is read only. The values
of VECTOR and PRIORITY should not be changed while IPIVPR n [A] is set.
0 No current interrupt activity associated with this source.
1 The interrupt bit for this source in the IPR or ISR is set.
Reserved
0 disables interrupt reporting from this source.
this interrupt resides in the interrupt request register (IRR) shown in
0
0
0
0
Figure 10-9. IPI Vector/Priority Register (IPIVPR n )
—
0
Table 10-13. IPIVPR n Field Descriptions
0
Table 10-12. PIR Field Descriptions
0
0
11 12
0
0
PRIORITY
0
0
15 16
0
Description
Description
Figure
0
0
0
10-9. There is one IPI vector/priority
0
0
Figure
0
0
VECTOR
10-48.
0
0
Freescale Semiconductor
0
0
Access: Read/Write
0
0
0
0
31
0