MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 418

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Programmable Interrupt Controller
Table 10-9
10.3.1.4
The global configuration register (GCR) shown in
allows software to reset the PIC.
Table 10-10
10-20
3–31
Bits Name
16–18
19–23
24–31
5–15
Offset 0x4_1020
Reset
Bits
0
1
2
0–4
W
R
RST Reset. Setting this field forces the PIC to be reset. Cleared automatically when the reset sequence is complete.
—
—
M
RST — M
NCPU Number of CPUs. The number of the highest physical CPU supported. This device implements one CPU (the
Name
NIRQ Number of interrupts. Contains the binary value of the maximum number of interrupt sources supported minus
0
VID
—
—
describes the FRR fields.
See
Reserved
Mode. PIC operating mode.
0 Pass-through mode. On-chip PIC is disabled and interrupts detected on IRQ0 are passed directly to the
1 Mixed mode. Interrupts are handled by the normal priority and delivery mechanisms of the PIC. See
Reserved
describes the GCR fields.
1
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
processor core. See
Section 10.1.4, “Modes of
Global Configuration Register (GCR)
Reserved.
one. The value is 79 (0x4F) because this device supports 80 interrupts: 12 external sources, 48 internal
sources (see
signaled sources. A zero in this field corresponds to one source.
Reserved.
processor core), referenced as P0.
Version ID. Version ID for this interrupt controller. Reports the OpenPIC specification revision level supported
by this implementation. A value of two corresponds to revision 1.2 which is the revision level currently
supported.
Section 10.4.8, “Reset of the
2
3
Table
Figure 10-6. Global Configuration Register (GCR)
Section 10.1.4, “Modes of
10-3), 4 timer sources, 4 IPI sources, 4 messaging sources, and 8 Shared message
Table 10-10. GCR Field Descriptions
Table 10-9. FRR Field Descriptions
Operation,” for more details.
PIC,” for more information.
Figure 10-6
All zeros
Description
Operation,” for more details.
Description
—
controls the PIC’s operating mode, and
Freescale Semiconductor
Access: Read/Write
31