MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 199

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.5
The e500 core is a pipelined, superscalar processor with parallel execution units that allow instructions to
execute out of order but record their results in order. Pipelining breaks instruction processing into discrete
stages, so multiple instructions in an instruction sequence can occupy the successive stages: as an
instruction completes one stage, it passes to the next, leaving the previous stage available to a subsequent
instruction. So, even though it may take multiple cycles for an instruction to pass through all of the pipeline
stages, once a pipeline is full, instruction throughput is much shorter than the latency.
A superscalar processor is one that issues multiple independent instructions into separate execution units,
allowing parallel execution. The e500 core has five execution units, one each for branch (BU), load/store
(LSU), and multiple-cycle operations (MU), and two for simple arithmetic operations (SU1 and SU2). The
MU and SU1 arithmetic execution units also execute 64-bit SPE vector instructions, using both the lower
and upper halves of the 64-bit GPRs.
The parallel execution units allow multiple instructions to execute in parallel and out of order. For
example, a low-latency addition instruction that is issued to an SU after an integer divide is issued to the
MU should finish executing before the higher latency divide instruction. The add instruction can make its
results available to a subsequent instruction, but it cannot update the architected GPR specified as its target
operand ahead of the multiple-cycle divide instruction.
5.5.1
The e500 core begins execution at fixed virtual address 0xFFFF_FFFC. The MMU has a default page
translation which maps this to the identical physical address. So, the instruction at physical address
0xFFFF_FFFC must be a branch to another address within the 4-Kbyte boot page.
5.5.2
To improve branch performance, the e500 provides implementation-specific dynamic branch prediction
using the BTB to resolve branch instructions and improve the accuracy of branch predictions. Each of the
512 entries in the 4-way set associative address cache of branch target addresses includes a 2-bit saturating
branch history counter, whose value is incremented or decremented depending on whether the branch was
taken. These bits can take on four values indicating strongly taken, weakly taken, weakly not taken, and
strongly not taken. The BTB is used not only to predict branches, but to detect branches during the fetch
stage, offering an efficient way to access instruction streams for branches predicted as taken.
In the e500, all branch instructions are assigned positions in the completion queue at dispatch. Speculative
instructions in branch target streams are allowed to execute and proceed through the completion queue,
although they can complete only after the branch prediction is resolved as correct and after the branch
instruction itself completes.
Freescale Semiconductor
Instruction Flow
Initial Instruction Fetch
Branch Detection and Prediction
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Branch Buffer Load Entry and Lock Set
Branch Buffer Entry Lock Reset
Table 5-5. BTB Locking Instructions
Name
Mnemonic
bblels
bbelr
Syntax
—
—
Core Complex Overview
5-13