MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 297

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.5
Table 7-23
assuming the core is running at 2 1/2 times the L2 cache frequency. The L2 returns the 128 bits containing
the requested data (critical quad word) first. This data is forwarded to the result register before the full
cache line reloads the L1.
7.6
This section explains the rules of cache and memory-mapped SRAM coherency. The term ‘snoop
transaction’ refers to transactions initiated by the system logic or by I/O traffic, as opposed to e500
core-initiated transactions.
Freescale Semiconductor
.
e500 core
load 1
e500 core
load 2
CCB
clocks
CCB addr
bus load 1
CCB addr
bus load 2
CCB data
bus
load 1
CCB data
bus
load 2
Clocks
Core
L2 Cache Timing
shows the timing of back-to-back loads that miss in the L1 data cache and hit in the L2 cache,
L2 Cache and SRAM Coherency
1
<1
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
2
3
BG
2
4
5
TS
3
6
Table 7-23. Fastest Read Timing—Hit in L2
7
BG
8
4
9
10
AACK
TS
5
11
12
COMING
DATA-
13
HIT
6
14
15
AACK
DATA
7
16
17
COMING
DATA-
DATA
18
HIT
8
19
20
DATA
L2 Look-Aside Cache/SRAM
9
21
22
DATA
23
10
24
25
11>
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