MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 101

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
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The e500 defines features that are not implemented on the MPC8544E. It also generally defines
features that the MPC8544E implements more specifically. An understanding of these differences
can be critical to ensure proper operations.
Section 1.3.1, “e500 Core Overview,”
256-Kbyte L2 cache/SRAM
— Flexible configuration. See
— Full ECC support on 64-bit boundary in both cache and SRAM modes
— Cache mode supports instruction caching, data caching, or both.
— External masters can force data to be allocated into the cache through programmed memory
— Eight-way set-associative cache organization (32-byte cache lines)
— Supports locking entire cache or selected lines. Individual line locks are set and cleared through
— Global locking and flash clearing done through writes to L2 configuration registers
— Instruction and data locks can be flash cleared separately.
— SRAM features include the following:
Address translation and mapping unit (ATMU)
— Ten local access windows define mapping within local 36-bit address space.
— Inbound and outbound ATMUs map to larger external address spaces.
DDR/DDR2 memory controller
— Programmable timing supporting DDR and DDR2 SDRAM
— 64-bit data interface
— Four banks of memory supported, each up to 4 Gbytes, to a maximum of 16 Gbytes
— DRAM chip configurations from 64 Mbits to 4 Gbits with x8/x16 data ports
— Full error checking and correction (ECC) support
— Page mode support
— Contiguous or discontiguous memory mapping
— Chip-select interleaving support
— Sleep mode support for self-refresh SDRAM
ranges or special transaction types (stashing).
– One, two, or four ways can be configured for stashing only
Book E instructions or by externally mastered transactions.
– I/O devices access SRAM regions by marking transactions as snoopable (global).
– Regions can reside at any aligned location in the memory map.
– Byte-accessible ECC is protected using read-modify-write transaction accesses for
– Three inbound windows plus a configuration window on PCI and PCI Express
– Four outbound windows plus default translation for PCI and PCI Express
– Up to 16 simultaneous open pages for DDR
– Up to 32 simultaneous open pages for DDR2
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
smaller-than-cache-line accesses.
Section 1.3.2, “On-Chip Memory Unit”
includes a comprehensive list of e500 core features.
Overview
1-3