MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 209

Manufacturer Part Number

BOARD DEVELOPMENT SYSTEM 8544

Manufacturer

Freescale Semiconductor

PowerQUICC III™r

Processor To Be Evaluated

Data Bus Width

Interface Type

Ethernet, I2C

Operating Supply Voltage

- 0.3 V to + 1.1 V

Leaded Process Compatible

Peak Reflow Compatible (260 C)

Rohs Compliant

For Use With/related Products

For Use With

PPC8544EVTANG - EVAL MPC8544 783FCPBGA

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

This two-level structure is shown in

Level-1 MMUs have the following features:

The level-2 MMU has the following features:

Freescale Semiconductor

Four-entry, fully associative TLB array that supports all nine page sizes

64-entry, 4-way set-associative TLB 4-Kbyte array that supports 4-Kbyte pages only

Hardware partially managed by L2 MMU

Supports snooping of TLBs by both internal and external tlbivax instructions

A 16-entry, fully associative L2 TLB array (TLB1) that supports all nine variable page sizes

TLB array (TLB0) that supports only 4-Kbyte pages, as follows:

— e500v1—256-entry, 2-way set-associative TLB array

— e500v2—512-entry, 4-way set-associative TLB array

Hardware assist for TLB miss exceptions

Software managed by tlbre, tlbwe, tlbsx, tlbsync, tlbivax, and mtspr instructions

Supports snooping of TLB by both internal and external tlbivax instructions

MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1

To instruction unit

To load/store unit

L1 Instruction MMU

32-Kbyte D-Cache

32-Kbyte I-Cache

Figure 5-8. MMU Structure