MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 292

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

L2 Look-Aside Cache/SRAM
Figure 7-20
Table 7-17
Figure 7-21
condition exists, the L2 signals an interrupt to the core through the internal int signal.
7-22
Offset 0x2_0E44
Reset
0–26
Offset 0x2_0E48
Reset
Bits
27
28
29
30
31
W
W
R
R
0
MBECCDIS Multiple-bit ECC error disable. Note that uncorrectable read errors may cause the assertion of
0
SBECCDIS Single-bit ECC error disable
L2CFGDIS
TPARDIS
Name
—
—
describes L2ERRDIS fields.
shows the L2 error disable register (L2ERRDIS).
shows the L2 error interrupt enable register (L2ERRINTEN). When an enabled error
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved
Tag parity error disable
0 Tag parity error detection enabled
1 Tag parity error detection disabled
core_fault_in , which causes the core to generate a machine check interrupt, unless it is disabled (by
clearing HID1[RFXE]). If RFXE is zero and this error occurs, MBECCDIS must be cleared and
L2ERRINTEN[MBECCINTEN] must be set to ensure that an interrupt is generated. For more information,
see
0 Multiple-bit ECC error detection enabled
1 Multiple-bit ECC error detection disabled
0 Single-bit ECC error detection enabled
1 Single-bit ECC error detection disabled
Reserved
L2 configuration error disable
0 L2 configuration error detection enabled
1 L2 configuration error detection disabled
Section 6.10.2, “Hardware Implementation-Dependent Register 1
Figure 7-21. L2 Error Interrupt Enable Register (L2ERRINTEN)
Figure 7-20. L2 Error Disable Register (L2ERRDIS)
—
—
Table 7-17. L2ERRDIS Field Descriptions
All zeros
All zeros
26
Description
TPARINTEN MBECCINTEN SBECCINTEN
26
27
TPARDIS MBECCDIS0 SBECCDIS — L2CFGDIS
27
28
28
(HID1).”
29
Freescale Semiconductor
29
Access: Read/Write
Access: Read/Write
—
30
30
L2CFGINTEN
31
31