MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 53
![BOARD DEVELOPMENT SYSTEM 8544](/photos/37/58/375876/mpc8544e_sml.jpg)
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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- Download datasheet (12Mb)
Figure
Number
12-73
12-74
12-75
12-76
12-77
12-78
12-79
12-80
12-81
12-82
12-83
12-84
12-85
13-1
13-2
13-3
13-4
13-5
13-6
13-7
13-8
13-9
13-10
13-11
13-12
13-13
13-14
13-15
13-16
14-1
14-2
14-3
14-4
14-5
14-6
14-7
14-8
14-9
14-10
14-11
14-12
Freescale Semiconductor
Base Registers (BRn) .......................................................................................................... 14-10
Header Dword Writeback Format ....................................................................................... 12-94
Crypto-Channel Pointer Status Register ............................................................................. 12-95
Crypto-Channel Current Descriptor Pointer Register ....................................................... 12-100
Fetch FIFO ........................................................................................................................ 12-101
Descriptor Buffer Format.................................................................................................. 12-102
Link Table Buffer .............................................................................................................. 12-103
EU Assignment Status Register (EUASR) ....................................................................... 12-109
Interrupt Status Register (ISR)...........................................................................................12-111
Interrupt Clear Register (ICR) .......................................................................................... 12-112
ID Register (ID) ................................................................................................................ 12-113
IP Block Revision Register ............................................................................................... 12-113
Master Control Register (MCR) ....................................................................................... 12-114
UART Block Diagram .......................................................................................................... 13-2
Receiver Buffer Registers (URBR0, URBR1)...................................................................... 13-6
Transmitter Holding Registers (UTHR0, UTHR1)............................................................... 13-7
Divisor Most Significant Byte Registers (UDMB0, UDMB1)............................................. 13-7
Divisor Least Significant Byte Registers (UDLB0, UDLB1)............................................... 13-8
Interrupt Enable Register (UIER) ......................................................................................... 13-9
Interrupt ID Registers (UIIR).............................................................................................. 13-10
FIFO Control Registers (UFCR0, UFCR1) ........................................................................ 13-11
Line Control Register (ULCR) ........................................................................................... 13-13
Modem Control Register (UMCR) ..................................................................................... 13-14
Line Status Register (ULSR) .............................................................................................. 13-15
Modem Status Register (UMSR) ........................................................................................ 13-16
Scratch Register (USCR) .................................................................................................... 13-17
Alternate Function Register (UAFR) .................................................................................. 13-17
DMA Status Register (UDSR) ............................................................................................ 13-18
UART Bus Interface Transaction Protocol Example .......................................................... 13-20
Local Bus Controller Block Diagram ................................................................................... 14-1
Option Registers (ORn) in GPCM Mode............................................................................ 14-13
Option Registers (ORn) in UPM Mode .............................................................................. 14-15
Option Registers (ORn) in SDRAM Mode......................................................................... 14-16
UPM Memory Address Register (MAR) ............................................................................ 14-17
UPM Mode Registers (MxMR)........................................................................................... 14-17
Memory Refresh Timer Prescaler Register (MRTPR)........................................................ 14-20
UPM Data Register (MDR) ................................................................................................ 14-20
SDRAM Machine Mode Register (LSDMR) ..................................................................... 14-21
UPM Refresh Timer (LURT) .............................................................................................. 14-23
LSRT SDRAM Refresh Timer (LSRT)............................................................................... 14-23
Interrupt Mask Register (IMR) ........................................................................................ 12-110
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Figures
Title
Number
Page
liii
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