MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 178
![BOARD DEVELOPMENT SYSTEM 8544](/photos/37/58/375876/mpc8544e_sml.jpg)
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
- Current page: 178 of 1340
- Download datasheet (12Mb)
Reset, Clocking, and Initialization
4.4.3.14
The eTSEC3 protocol inputs, shown in
the eTSEC3 controller. Note that the value latched on these signals during POR is accessible through the
memory-mapped PORDEVSR (POR device status register) described in
Status Register (PORDEVSR).”
4.4.3.15
As shown in
clock--either a 100MHz or 125MHz LVDS differential clock. This one clock is applied to an internal PLL
whose output creates the clock used by all four SGMII SerDes lanes. The result is always a 1.25Gbaud
transmission/receive rate on each lane. Note that the value latched on this signal is accessible through the
memory-mapped SerDes Control and Status Register described in
Register 3
4-20
TSEC1_TXD[0:1]
Functional Signal
TSEC3_TXD[0:1]
Default (11)
Functional
Default (11)
Signal
(SRDS2CR3).”
Table
eTSEC3 Protocol
SGMII SerDes Reference Clock Configuration
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reset Configuration
cfg_tsec1_prtcl[0:1]
Reset Configuration
cfg_tsec3_prtcl[0:1]
4-24, two options are available for the frequency of the input SGMII SerDes reference
Name
Name
Table 4-22. eTSEC1 Protocol Configuration
Table 4-23. eTSEC3 Protocol Configuration
(Binary)
Value
(Binary)
00
01
10
11
Value
00
01
10
11
Table
The eTSEC1 controller operates using 8-bit FIFO protocol.
The eTSEC1 controller operates using the MII protocol (or RMII if
configured in reduced mode as described in
width”).
The eTSEC1 controller operates using the GMII protocol (or RGMII if
configured in reduced mode as described in
width”).
The eTSEC1 controller operates using the TBI protocol (or RTBI if
configured in reduced mode as described in
width”) (default).
The eTSEC3 controller operates using 8-bit FIFO protocol.
The eTSEC3 controller operates using the MII protocol (or RMII if
configured in reduced mode as described in
Width”)
The eTSEC3 controller operates using the GMII protocol (or RGMII if
configured in reduced mode as described in
Width”).
The eTSEC3 controller operates using the TBI protocol (or RTBI if
configured in reduced mode as described in
Width”) (default).
4-23, select the protocol (FIFO, MII, GMII or TBI) used by
Section 19.4.1.26, “SerDes 2 Control
Meaning
Meaning
Section 19.4.1.4, “POR Device
Section 4.4.3.11, “eTSEC1
Section 4.4.3.11, “eTSEC1
Section 4.4.3.11, “eTSEC1
Section 4.4.3.12, “eTSEC3
Section 4.4.3.12, “eTSEC3
Section 4.4.3.12, “eTSEC3
Freescale Semiconductor
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