MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 603

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 13-3
Table 13-5
13.3.1.3
The divisor least significant byte register (UDLB) is concatenated with the divisor most significant byte
register (UDMB) to create the divisor used to divide the input clock into the DUART. The output frequency
of the baud generator is 16 times the baud rate; therefore the desired baud rate = platform clock frequency
/ (16 × [UDMB||UDLB]). Equivalently, [UDMB||UDLB:0b0000] = platform clock frequency / desired
baud rate. Baud rates that can be generated by specific input clock frequencies are shown in
Figure 13-4
Table 13-6
Freescale Semiconductor
Bits
Bits
0–7
0–7
Offset 0x500
Offset 0x501
Reset
Reset
UDMB Divisor most-significant byte
Name
Name
DATA
W
W
R
R
describes the fields of UTHR.
describes the fields of UDMB registers.
shows the bits in the UTHRs.
shows the bits in the UDMBs.
0x600
0x601
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
(ULCR[DLAB] = 1)
Data that is written to UTHR (write only)
Divisor Most and Least Significant Byte Registers (UDMB and UDLB)
Figure 13-4. Divisor Most Significant Byte Registers (UDMB0, UDMB1)
0
0
Figure 13-3. Transmitter Holding Registers (UTHR0, UTHR1)
Table 13-6. UDMB Field Descriptions
Table 13-5. UTHR Field Descriptions
All zeros
All zeros
UDMB
Description
Description
Access: Read/Write
Access: Write only
Table
7
7
13-8.
DUART
13-7