MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 38

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Paragraph
Number
18.3.6.1
18.3.6.2
18.3.6.3
18.3.6.4
18.3.6.5
18.3.6.6
18.3.6.7
18.3.6.8
18.3.7
18.3.7.1
18.3.7.1.1
18.3.7.1.2
18.3.7.2
18.3.8
18.3.8.1
18.3.8.1.1
18.3.8.1.2
18.3.8.1.3
18.3.8.1.4
18.3.8.1.5
18.3.8.1.6
18.3.8.1.7
18.3.8.1.8
18.3.8.1.9
18.3.8.1.10
18.3.8.2
18.3.8.2.1
18.3.8.2.2
18.3.8.2.3
18.3.8.2.4
18.3.8.2.5
18.3.8.2.6
18.3.8.2.7
18.3.8.2.8
18.3.8.3
18.3.8.3.1
18.3.8.3.2
18.3.8.3.3
18.3.8.3.4
18.3.8.3.5
18.3.8.3.6
xxxviii
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
PCI Express Configuration Space Access ............................................................... 18-42
PCI Compatible Configuration Headers .................................................................. 18-43
PCI Express Error Detect Register (PEX_ERR_DR).......................................... 18-29
PCI Express Error Interrupt Enable Register (PEX_ERR_EN) .......................... 18-32
PCI Express Error Disable Register (PEX_ERR_DISR) .................................... 18-34
PCI Express Error Capture Status Register (PEX_ERR_CAP_STAT) ............... 18-35
PCI Express Error Capture Register 0 (PEX_ERR_CAP_R0)............................ 18-36
PCI Express Error Capture Register 1 (PEX_ERR_CAP_R1)............................ 18-38
PCI Express Error Capture Register 2 (PEX_ERR_CAP_R2)............................ 18-39
PCI Express Error Capture Register 3 (PEX_ERR_CAP_R3)............................ 18-40
RC Configuration Register Access...................................................................... 18-42
EP Configuration Register Access....................................................................... 18-43
Common PCI Compatible Configuration Header Registers................................ 18-44
Type 0 Configuration Header .............................................................................. 18-50
Type 1 Configuration Header .............................................................................. 18-56
PCI Express Configuration Access Register Mechanism................................ 18-42
Outbound ATMU Configuration Mechanism (RC-Only) ............................... 18-42
PCI Express Vendor ID Register—Offset 0x00 .............................................. 18-44
PCI Express Device ID Register—Offset 0x02............................................... 18-44
PCI Express Command Register—Offset 0x04 .............................................. 18-44
PCI Express Status Register—Offset 0x06 ..................................................... 18-46
PCI Express Revision ID Register—Offset 0x08............................................ 18-47
PCI Express Class Code Register—Offset 0x09 ............................................. 18-47
PCI Express Cache Line Size Register—Offset 0x0C .................................... 18-48
PCI Express Latency Timer Register—0x0D.................................................. 18-49
PCI Express Header Type Register—0x0E ..................................................... 18-49
PCI Express BIST Register—0x0F ................................................................. 18-50
PCI Express Base Address Registers—0x10–0x27......................................... 18-50
PCI Express Subsystem Vendor ID Register (EP-Mode Only)—0x2C .......... 18-53
PCI Express Subsystem ID Register (EP-Mode Only)—0x2E ....................... 18-53
Capabilities Pointer Register—0x34 ............................................................... 18-54
PCI Express Interrupt Line Register (EP-Mode Only)—0x3C ....................... 18-54
PCI Express Interrupt Pin Register—0x3D..................................................... 18-55
PCI Express Minimum Grant Register (EP-Mode Only)—0x3E ................... 18-55
PCI Express Maximum Latency Register (EP-Mode Only)—0x3F ............... 18-56
PCI Express Base Address Register 0—0x10 ................................................. 18-57
PCI Express Primary Bus Number Register—Offset 0x18 ............................. 18-57
PCI Express Secondary Bus Number Register—Offset 0x19......................... 18-58
PCI Express Subordinate Bus Number Register—Offset 0x1A...................... 18-58
PCI Express Secondary Latency Timer Register—0x1B ................................ 18-59
PCI Express I/O Base Register—0x1C ........................................................... 18-59
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