MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 852
![BOARD DEVELOPMENT SYSTEM 8544](/photos/37/58/375876/mpc8544e_sml.jpg)
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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Enhanced Three-Speed Ethernet Controllers
Table 15-114
15-120
11–15
Bits
2–3
4–6
7–8
10
9
PAUSE
Remote
Duplex
Duplex
Name
Pause
0
0
Fault
Local Device
Half
Full
—
—
describes the resolution of pause priority.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
ASM_DIR
The local device’s remote fault condition is encoded in bits 2 and 3 of the base page. Values are shown in
the following table. The default value is 00. Indicate a fault by setting a non-zero remote fault encoding and
re-negotiating.
Reserved, should be cleared.
The local device’s PAUSE capability is encoded in bits 7 and 8, and the decodes are shown in the following
table. For priority resolution information consult
Half-duplex capability.
0 Designates local device as not capable of half-duplex operation.
1 Designates local device as capable of half-duplex operation.
Full-duplex capability.
0 Designates the local device as not capable of full-duplex operation.
1 Designates the local device as capable of full-duplex operation.
Reserved, should be cleared.
PAUSE bit[8]
0
1
0
0
1
1
RF1 bit[3]
Table 15-113. ANA Field Descriptions (continued)
PAUSE
0
0
1
1
x
0
Link Partner
ASM_DIR bit[7]
Table 15-114. PAUSE Priority Resolution
ASM_DIR
0
1
0
1
RF2 bit[2]
x
x
0
1
0
1
No PAUSE
Asymmetric PAUSE toward link partner
Symmetric PAUSE
Both symmetric PAUSE and
Asymmetric PAUSE toward local device
Disable PAUSE transmit
Disable PAUSE receive
Disable PAUSE transmit
Disable PAUSE receive
No error, link OK
Offline
Link_Failure
Auto-Negotiation_Error
Local Resolution
Description
Table
15-114.
Description
Capability
Disable PAUSE transmit
Disable PAUSE receive
Disable PAUSE transmit
Disable PAUSE receive
Link Partner Resolution
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