MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 802

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
15-70
Bits
25
26
27
28
29
PreAM TxEN User defined preamble enable for transmitted frames. This bit is cleared by default.
PAD/CRC
Length
Frame
MPEN
Name
check
Huge
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
0 The MAC generates a standard Ethernet preamble.
1 If a user-defined preamble has been passed to the MAC it is transmitted instead of the standard
Huge frame enable. This bit is cleared by default.
0 Limit the length of frames received to less than or equal to the maximum frame length value
1 Frames are transmitted and received regardless of their relationship to the maximum frame length.
Note that if Huge Frame is cleared, the user must ensure that adequate buffer space is allocated for
Length check. This bit is cleared by default.
0 No length field checking is performed.
1 The MAC checks the frame’s length field on receive to ensure it matches the actual data field length.
Magic packet enable for Ethernet modes. This bit is cleared by default. MPEN should be enabled only
after GRACEFUL RECEIVE STOP and GRACEFUL TRANSMIT STOP are completed successfully (in
other words, transmission and reception have stopped).
0 Normal receive behavior on receive, or Magic Packet mode has exited with reception of a valid
1 Commence Magic Packet detection by the MAC provided that frame reception is enabled in
Pad and append CRC. This bit is cleared by default.
0 Frames presented to the MAC have a valid length and contain a CRC.
1 The MAC pads all transmitted short frames and appends a CRC to every frame regardless of
preamble. Otherwise the standard Ethernet preamble is generated. The Preamble Length field
should be left at its default setting if a user-defined preamble is transmitted. Not applicable to FIFO
or RMII 10/100 modes.
(MAXFRM[Maximum Frame]) and limit the length of frames transmitted to less than the maximum
frame length.
See
received frames. See
information.
Transmitted frames are not checked.
Magic Packet.
MACCFG1. In this mode the MAC ignores all received frames until the specific Magic Packet frame
is received, at which point this bit is cleared by the eTSEC, and a maskable interrupt via
IEVENT[MAG] occurs.
padding requirement.
Receive or transmit > maximum frame length
Receive
Transmit
Receive or transmit < maximum frame length
Table 15-40. MACCFG2 Field Descriptions (continued)
Section 15.6.7, “Buffer
Frame type
Section 15.5.3.5.5, “Maximum Frame Length Register
= maximum frame length
= maximum frame length
Descriptors,” for further details of buffer descriptor bit updating.
Frame length
Description
truncation
Packet
yes
no
no
no
Freescale Semiconductor
Buffer descriptor
(MAXFRM),” for further
updated
yes
yes
no
no