MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 176
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MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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- Download datasheet (12Mb)
Reset, Clocking, and Initialization
4.4.3.9
DDR1 requires a different voltage level from DDR2.
SDRAM type.
4.4.3.10
The eTSEC1 and eTSEC2 Serial inputs, shown in
eTSEC3 respectively. Note that the value latched on this signal during POR is accessible through the
memory-mapped PORDEVSR (POR device status register) described in
Status Register (PORDEVSR).”
These values supersede the width and protocol definitions set by other POR config inputs defined below
that describe the parallel eTSEC interfaces.
4-18
TSEC1_TXD[2]
TSEC3_TXD[2]
LGPL0, LGPL1
Functional
Functional
Default (1)
Default (1)
Default (11)
Functional
Signal
Signal
Signal
DDR SDRAM Type
eTSEC1 Serial GMII and eTSEC3 Serial GMII
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reset Configuration
Reset Configuration
cfg_tsec1_serial
cfg_tsec3_serial
Reset Configuration
cfg_dram_type[0:1]
Name
Name
Name
Table 4-18. eTSEC1 Serial Configuration
Table 4-19. eTSEC3 Serial Configuration
(Binary)
(Binary)
Value
Value
0
0
1
1
Table 4-17. DDR DRAM Type
(Binary)
Value
00
01
10
11
eTSEC1 Ethernet interface operates in serial SGMII mode. POR config
eTSEC3 Ethernet interface operates in serial SGMII mode. POR config
inputs cfg_tsec1_width and cfg_tsec1_prtcl should be left in their default
settings.
eTSEC1 Ethernet interface uses parallel interface according to POR config
inputs cfg_tsec1_width and cfg_tsec1_prtcl.
(default).
inputs cfg_tsec3_width and cfg_tsec3_prtcl should be left in their default
settings.
eTSEC3 Ethernet interface uses parallel interface according to POR config
inputs cfg_tsec3_width and cfg_tsec3_prtcl.
(default).
DDR1
2.5V, CKE low at reset
Reserved
DDR2
1.8V, CKE low at reset (default)
Reserved
Table
Table 4-17
4-21, selects SGMII protocol for eTSEC1 and
describes the configuration of the DDR
Meaning
Meaning
Meaning
Section 19.4.1.4, “POR Device
Freescale Semiconductor
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