MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 590

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 2.1
12.6.5.2
The SEC controller generates the single interrupt output from all possible interrupt sources. These sources
can be individually enabled by the interrupt mask register. If enabled, the interrupt source value, when
active, is captured into the interrupt status register.
interrupt source. Each interrupt source is individually enabled by setting its corresponding bit. At reset, all
bits are disabled. The bit fields are described in
Table 12-60
interrupt clear register.
12-110
20–23
I
Bits
Address 0x3_1008
15
Reset
Reset
Reset
Reset
W
W
W
W
R
R
R
R
Table 12-60. Field Names in Interrupt Mask, Interrupt Status, and Interrupt Clear Registers
Overflow
Name
Done
16
32
48
0
ITO
describes the register field names in the interrupt mask register, interrupt status register, and
Interrupt Mask Register (IMR)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
—
49
—
Internal time out.
0 No internal time out
1 An internal time out was detected
The internal time out interrupt is triggered by the controller if a slave access to an SEC register does
not result in successful data transfer within 16 clock cycles. With ITO enabled the SEC controller
terminates the transaction and signals and interrupt.
Done overflow.
0 No done overflow
1 Done overflow error. Indicates that more than 15 done interrupts were queued from the interrupting
channel without an interrupt clear.
Err
50
AFEU
—
Dn
19
51
Figure 12-80. Interrupt Mask Register (IMR)
CH4
20
52
—
DONE Overflow
CH3
21
37
53
CH2
Err
Err
22
38
54
Table
MDEU
KEU
Figure 12-80
CH1
Dn
Dn
—
23
39
55
All zeros
All zeros
All zeros
All zeros
12-60.
Description
Err
24
40
56
CHN_4
—
—
shows the bit positions of each potential
Dn
25
41
57
Err
Err
Err
26
42
58
CHN_3
PKEU
AESU
Dn
Dn
Dn
27
43
59
Err
28
44
60
CHN_2
Freescale Semiconductor
—
—
Access: Read/write
Dn
29
45
61
Err
Err
Err
14
30
46
62
CHN_1
RNG
DEU
ITO
Dn
Dn
Dn
15
31
47
63