MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 650

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Local Bus Controller
14.3.1.16
The clock ratio register sets the system (CCB) clock to LBC bus frequency ratio. It also provides
configuration bits for extra delay cycles for address and control signals.
14-30
11–13
16–23
24–31
Bits
8–9
10
14
15
Offset 0x0D4
Reset
W
R
BCTLC Defines the use of LBCTL
LPBSE Enables parity byte select on LGTA/LGPL4/LUPWAIT/LPBSE signal.
Name
EPAR Determines odd or even parity. Writing the memory with EPAR = 1 and reading the memory with EPAR = 0
AHD
BMT
PBYP — BUFCMDC
—
—
1
0
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Clock Ratio Register (LCRR)
00 LBCTL is used as W/R control for GPCM or UPM accesses (buffer control).
01 LBCTL is used as LOE for GPCM accesses only.
10 LBCTL is used as LWE for GPCM accesses only.
11 Reserved.
Address hold disable. Removes part of the hold time for LAD with respect to LALE in order to lengthen the
LALE pulse
0 During address phases on the local bus, the LALE signal negates two platform clock periods prior to the
1 During address phases on the local bus, the LALE signal negates one platform clock period prior to the
Reserved
0 Parity byte select is disabled. LGTA/LGPL4/LUPWAIT/LPBSE signal is available for memory control as
1 Parity byte select is enabled. LGTA/LGPL4/LUPWAIT/LPBSE signal is dedicated as the parity byte select
generates parity errors for testing.
0 Odd parity
1 Even parity
Bus monitor timing. Defines the bus monitor time-out period. Clearing BMT (reset value) selects the maximum
count of 2048 bus clock cycles. For non-zero values of BMT, the number of LCLK clock cycles to count down
before a time-out error is generated is given by: bus cycles = BMT x 8.
Apart from BMT = 0x00, the minimum value of BMT is 5, corresponding with 40 bus cycles. Shorter time-outs
may result in spurious errors during SDRAM operation.
Reserved
1
0
address being invalidated. At 666 MHz, this provides 3 ns of additional address hold time at the external
address latch.
address being invalidated. This halves the address hold time, but extends the latch enable duration. This
may be necessary for very high frequency designs.
LGPL4 (output) or LGTA/LUPWAIT (input).
output, and LGTA/LUPWAIT is disabled.
0
2
0
3
Table 14-21. LBCR Field Descriptions (continued)
0 0 0 0 0 0 0 0 0 0 0
4
—
Figure 14-19. Clock Ratio Register (LCRR)
5
6
ECL
7
8
—
13 14 15 16
Description
EADC
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
—
Freescale Semiconductor
Access: Read/Write
27 28
CLKDIV
31