MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 921

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 15-155
Table 15-156
Freescale Semiconductor
eTSEC Signals
GTX_CLK125
Set up the MII Mgmt for a read cycle to TBI Control register (write the TBI address and Register address),
MDIO
MDC
set source clock divide by 14 for example to insure that MDC clock speed is not greater than 2.5 MHz
Sum
describes the shared signals for the TBI interface.
describes the register initializations required to configure the eTSEC in TBI mode.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
I/O
I/O
O
MACSTNADDR2[0110_0000_0000_0010_0000_0000_0000_0000]
MACSTNADDR1[0100_0011_0110_0101_1000_0111_1000_1100]
I
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
MACCFG1[1000_0000_0000_0000_0000_0000_0000_0000]
MACCFG1[0000_0000_0000_0000_0000_0000_0000_0000]
MACCFG2[0000_0000_0000_0000_0111_0010_0000_0101]
Table 15-156. TBI Mode Register Initialization Steps
The TBI Control register is at offset address 0x0 from TBIPA.
MIIMCFG[0000_0000_0000_0000_0000_0000_0000_0101]
MIIMADD[0000_0000_0000_0000_0001_0000_0000_0000]
ECNTRL[0000_0000_0000_0000_0001_0000_0000_0000]
Read MII Mgmt Indicator register and check for Busy = 0,
TBIPA[0000_0000_0000_0000_0000_0000_0001_0000]
Signals
This indicates that the eTSEC MII Mgmt bus is idle.
No. of
1
1
1
(This example has Statistics Enable = 1)
Table 15-155. Shared TBI Signals
Assign a Physical address to the TBI,
Setup the MII Mgmt clock speed,
to 02608C:876543, for example.
to 02608C:876543, for example.
(I/F Mode = 2, Full Duplex = 1)
Initialize MAC Station Address
Initialize MAC Station Address
set to 16, for example.
GTX_CLK125
GMII Signals
Initialize MACCFG2,
Initialize ECNTRL,
Clear Soft_Reset,
Set Soft_Reset,
MDIO
MDC
Sum
I/O
I/O
O
I
Signals
No. of
Enhanced Three-Speed Ethernet Controllers
1
1
1
Management interface clock
Management interface I/O
Reference clock
Function
15-189