MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 680

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Local Bus Controller
A UPM refresh timer request pattern initiates a refresh timer pattern (RTS).
An exception (caused by a bus monitor time-out error) occurring while another UPM pattern is running
initiates an exception condition pattern (EXS).
Figure 14-54
cycle type. RUN commands (MxMR[OP] = 11), however, can initiate patterns starting at any of the 64
UPM RAM words.
14.4.4.1.1
The user must ensure that the UPM is appropriately initialized before a request occurs.
The UPM supports two types of memory reads and writes:
14-60
•
•
A single-beat transfer transfers one operand consisting of up to a single word (dependent on port
size). A single-beat cycle starts with one transfer start and ends with one transfer acknowledge.
A burst transfer transfers exactly 4 double words regardless of port size. For 32-bit accesses, the
burst cycle starts with one transfer start but ends after eight transfer acknowledges, whereas an
8-bit device requires 32 transfer acknowledges.
Exception Condition Request
and
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Read Single-Beat Request
Write Single-Beat Request
Memory Access Requests
Table 14-27
Refresh Timer Request
Read Burst Request
Write Burst Request
Read single-beat (RSS)
Read burst (RBS)
Write single-beat (WSS)
Write burst (WBS)
Refresh timer (RTS)
Exception condition (EXS)
show the start addresses of these patterns in the UPM RAM, according to
Table 14-27. UPM Routines Start Addresses
UPM Routine
Figure 14-54. RAM Array Indexing
Array Index
Generator
WSS
WBS
RSS
RBS
EXS
Routine Start Address
RTS
0x3C
0x00
0x08
0x18
0x20
0x30
RAM Array
Freescale Semiconductor
64 RAM
Words