MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 688
![BOARD DEVELOPMENT SYSTEM 8544](/photos/37/58/375876/mpc8544e_sml.jpg)
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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- Download datasheet (12Mb)
Local Bus Controller
signal of the corresponding bank depends on the value of each CSTn bit.
control LCSn signals.
14.4.4.4.3
If BRn[MSEL] of the accessed memory bank selects a UPM on the currently requested cycle, the selected
UPM affects the assertion and negation of the appropriate LBS[0:3] signal. The timing of all four
byte-select signals is specified in the RAM word. However, LBS[0:3] are also controlled by the port size
of the accessed bank, the number of bytes to transfer, and the address accessed.
Figure 14-60
The uppermost byte select (LBS0), when asserted, indicates that LAD[0:7] contains valid data during a
cycle. Likewise, LBS1 indicates that LAD[8:15] contains valid data, LBS2 indicates that LAD[16:23]
contains valid data, and LBS3 indicates that LAD[24:31] contains valid data. For a UPM refresh timer
request, all LBS[0:3] signals are asserted/negated by the UPM according to the refresh pattern only.
14-68
shows how UPMs control LBS[0:3].
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Byte Select Signal Timing (BST n )
UPMA/B/C
SDRAM
UPMA
UPMB
UPMC
GPCM
Figure 14-59. LCS n Signal Selection
Figure 14-60. LBS Signal Selection
BR n [MSEL]
MUX
Bank Selected
BR n [MSEL]
Bank Selected
MUX
BR n [PS]
Byte-Select
Byte count
Logic
Switch
A[29:31]
Figure 14-59
LCS0
LCS1
LCS2
LCS3
LCS4
LCS5
LCS6
LCS7
LBS0
LBS1
LBS2
LBS3
Freescale Semiconductor
shows how UPMs
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