MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 243
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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- Download datasheet (12Mb)
6.10
6.10.1
Freescale Semiconductor
Reset
Reset
33–39
43–48
51–55
SPR 1008
Bits
32
40
41
42
49
50
W
W
R
R
EMCP
—
32
48
SEL_TBCLK Select time base clock. If the time base is enabled, this field functions as follows:
SLEEP
EMCP
Name
DOZE
TBEN
Hardware Implementation-Dependent Registers
NAP
—
—
—
TBEN SEL_TBCLK
Hardware Implementation-Dependent Register 0 (HID0)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
33
49
Figure 6-32. Hardware Implementation-Dependent Register 0 (HID0)
Enable machine check pin, MCP. Used to mask out further machine check exceptions caused by
assertion of MCP.
0 MCP is disabled.
1 MCP is enabled. If MSE[ME] = 0, asserting MCP causes checkstop. If MSR[ME] = 1, asserting MCP
Reserved, should be cleared.
Doze power management mode. If MSR[WE] is set, this bit controls DOZE mode.
0 Core not in doze mode
1 Core in doze mode
Nap power management mode. If MSR[WE] is set, this bit controls NAP mode.
0 Core not in nap mode
1 Core in nap mode
Configure for sleep power management mode. Controls SLEEP mode if MSR[WE] is set.
0 Core not in sleep mode
1 Core in sleep mode
Reserved, should be cleared.
Time base enable
0 Time base disabled (no counting)
1 Time base enabled
0 Time base is based on the processor clock
1 Time base is based on the TBCLK (RTC) input
Reserved, should be cleared.
• If HID0[TBEN] = 1 and HID0[SEL_TBCLK] = 0, the time base is updated every 8 bus clocks
• If HID0[TBEN] = 1 and HID0[SEL_TBCLK] = 1, the time base is updated on the rising edge of
causes a machine check exception.
core_tbclk (sampled at bus rate). The maximum supported frequency can be found in the electrical
specifications, but this value is approximately 25% of the bus clock frequency.
50
—
51
Table 6-18. HID0 Field Descriptions
—
39
55
EN_MAS7_UPDATE DCFA
All zeros
All zeros
DOZE
40
56
Description
NAP SLEEP
41
57
42
58
43
Access: Supervisor read/write
—
Core Register Summary
—
62
NOPTI
47
63
6-25
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