MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 930

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
15-198
Set up the MII Mgmt for a write cycle to the external PHY Control register (write the PHY address and Register address),
This enables the external PHY to restart Auto-Negotiations using the configuration set in the AN Advertisement register.
Other information about the link is also returned. (Extend Status, No pre, Remote Fault, An Ability, Link status, extend
Set up the MII Mgmt for a read cycle to the PHY MII Mgmt register (write the PHY address and Register address),
Setting up the MII Mgmt for a write cycle to TBI MII Mgmt register (write the TBI’s address and Register address),
read the MII Mgmt AN Link Partner Base Page Ability register and check bits 9 and 10. (Half and Full Duplex)
Writing to MII Mgmt Control with 16-bit data intended for TBI’s MII Mgmt control register (TBI control),
MII Mgmt AN Link Partner Base Page Ability ---> [0000_0000_0000_0000_0000_000x_x110_0000]
The Control register is at offset address 0x00 from the external PHY address. (in this case 0x11)
read the MII Mgmt AN Expansion register and check bits 13 and 14. (NP Able and Page Rx’d)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Perform an MII Mgmt read cycle of AN Link Partner Base Page Ability Register. (Optional)
Write to MII Mgmt Control with 16-bit data intended for the external PHY Control register,
(Uses the PHY address (0x11) and Register address (6) placed in MIIMADD register)
(Uses the PHY address (0x11) and Register address (5) placed in MIIMADD register)
The PHY Status register is at address 0x1 and in this case the PHY Address is 0x2.
(Uses the PHY address (2) and Register address (1) placed in MIIMADD register)
MII Mgmt AN Expansion ---> [0000_0000_0000_0000_0000_0000_0000_0110]
Table 15-162. RMII Mode Register Initialization Steps (continued)
Setup MIIMADD[0000_0000_0000_0000_0001_0001_0000_0110]
Setup MIIMADD[0000_0000_0000_0000_0001_0001_0000_0101]
MIIMSTAT ---> [0000_0000_0000_0000_0000_0000_0010_0000]
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
MIIMCON[0000_0000_0000_0000_0001_0010_0000_0000]
MIIMCON[0000_0000_0000_0000_0000_0010_0001_0000]
MIIMADD[0000_0000_0000_0000_0001_0001_0000_0000]
MIIMADD[0000_0000_0000_0000_0000_0010_0000_0001]
MIIMADD[0000_0000_0000_0000_0001_0000_0000_1011]
the TBI control register is at offset address 0x11 from TBIPA
This configures the TBI control to GMII mode and AN sense
Perform an MII Mgmt read cycle of AN Expansion Register.
Read MII Mgmt Indicator register and check for Busy = 0,
Read MII Mgmt Indicator register and check for Busy = 0,
read the MIIMSTAT register and check bit 10. (AN Done)
Check to see if PHY has completed Auto-Negotiation.
Perform an MII Mgmt write cycle to the external PHY.
Perform an MII Mgmt read cycle of Status Register.
This indicates that the write cycle was completed.
This indicate that the write cycle was completed
Check to see if MII Mgmt write is complete.
Check to see if MII Mgmt write is complete
Perform an MII Mgmt write cycle
Clear MIIMCOM[Read Cycle]
Clear MIIMCOM[Read Cycle]
Clear MIIMCOM[Read Cycle]
Set MIIMCOM[Read Cycle]
Set MIIMCOM[Read Cycle]
Set MIIMCOM[Read Cycle]
When MIIMIND[BUSY]=0,
When MIIMIND[BUSY]=0,
When MIIMIND[BUSY]=0,
Ability)
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