MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 152

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Signal Descriptions
3-12
PCI_C/BE[3:0]
LSSD_MODE
LSYNC_OUT
PCI_AD[31:0]
MSRCID[2:4]
LSYNC_IN
MCKE[0:3]
MDQ[0:63]
MDQS[0:7]
MDQS[0:8]
MECC[0:7]
MODT[0:3]
MCK[0:5],
MDIC[0:1]
MSRCID0
MSRCID1
LWE[1:3]/
MDM[0:7]
MBA[2:0]
MCK[0:5]
MCS[0:3]
PCI_CLK
MA[15:0]
LBS[1:3]
MDQS8
MDVAL
LGPL5
MCAS
MDM8
MRAS
Name
LWE0
/LBS0
MWE
MCP
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Local bus GP line 5 address
LSSD mode
Local bus DLL synchronization
Local bus DLL synchronization
Local bus write enable
/byte select 1–3
Local bus write enable
/byte select 0
DDR address
DDR bank select
DDR column address strobe
DDR differential clocks (3
pairs/DIMM)
DDR clock enable
Machine check processor
DDR chip select (2/DIMM)
Driver impedence calibration
DDR data mask
DDR ECC data mask
DDR data
DDR data strobe
DDR ECC data strobe
(complement)
DDR ECC data strobe
Memory debug data valid
DDR error correcting code
DRAM On-Die Termination
DDR row address strobe
Memory debug source port ID
2–4
Memory debug source port ID 0
Memory debug source port ID 1
DDR write enable
PCI address/data
PCI command/byte enable
PCI clock
Table 3-2. MPC8544E Alphabetical Signal Reference (continued)
Description
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
Functional
Debug/
Debug
Debug
Debug
Debug
Block
LBC
LBC
LBC
LBC
LBC
Test
PIC
PCI
PCI
PCI
Alternate Function(s)
cfg_host_agt[0:2]
cfg_mem_debug
cfg_boot_seq[1]
cfg_ddr_debug
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Signals
No. of
16
12
64
32
1
1
1
1
3
1
3
1
4
1
4
2
8
1
8
9
1
1
8
4
1
3
1
1
1
4
1
Freescale Semiconductor
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
14-2/14-5
21-5/21-8
14-2/14-5
14-2/14-5
14-2/14-5
14-2/14-5
10-5/10-8
21-3/21-7
21-3/21-7
21-3/21-7
21-3/21-7
17-2/17-6
17-2/17-6
17-2/17-6
9-3/9-5
9-3/9-5
9-3/9-5
9-3/9-5
9-3/9-5
9-3/9-5
9-3/9-5
9-3/9-5
9-3/9-5
9-3/9-5
9-3/9-5
9-3/9-5
9-3/9-5
9-3/9-5
9-3/9-5
Table/
Page