MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 284

Manufacturer Part Number

BOARD DEVELOPMENT SYSTEM 8544

Manufacturer

Freescale Semiconductor

PowerQUICC III™r

Processor To Be Evaluated

Data Bus Width

Interface Type

Ethernet, I2C

Operating Supply Voltage

- 0.3 V to + 1.1 V

Leaded Process Compatible

Peak Reflow Compatible (260 C)

Rohs Compliant

For Use With/related Products

For Use With

PPC8544EVTANG - EVAL MPC8544 783FCPBGA

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

L2 Look-Aside Cache/SRAM

The L2 cache external write address registers extended address (L2CEWAREAn), shown in

contain the upper 4 bits of the 28-bit L2 cache external write base address.

The L2CEWARn/L2CEWAREAn address registers work with the L2 cache external write control

registers 0–3 (L2CEWCRn), shown in

Offset 0x2_0014

Offset 0x2_0018

Figure 7-9. Cache External Write Address Registers Extended Address (L2CEWAREA n )

describes L2CEWARn fields.

describes the fields of L2CEWAREAn.

Figure 7-10. Cache External Write Control Registers (L2CEWCR0–L2CEWCR3)

MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1

L2 Cache External Write Address Registers Extended Address 0–3

(L2CEWAREA n )

L2 Cache External Write Control Registers 0–3 (L2CEWCR n )

bits of the base address are in L2CEWAREA n [ADDR].

address is in L2CEWAR n [ADDR].

Contains the lower 24 bits of the 28-bit L2 cache external write base address. Note that the upper 4

Contains the upper 4 bits of the L2 cache external write base address. Note that the rest of the base

Table 7-6. L2CEWAREA n Field Descriptions

Table 7-5. L2CEWAR n Field Descriptions

7-10, to control cache external write functionality.

Freescale Semiconductor

Access: Read/Write