MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 437
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MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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- Download datasheet (12Mb)
Table 10-39
10.3.7
The interrupt source configuration registers control the source of each interrupt, specifying parameters
such as the interrupting event, signal polarity, and relative priority.
10.3.7.1
The external interrupt vector/priority registers (EIVPRs) contain polarity and sense fields for the external
interrupts caused by the assertion of any of IRQ[0:11]. The format of the EIVPRs is shown in
Figure
Table 10-40
Freescale Semiconductor
Offset EIVPR0: 0x5_0000, EIVPR1: 0x5_0020, EIVPR2: 0x5_0040, EIVPR3: 0x5_0060, EIVPR4: 0x5_0080,
Reset
Bits
2–7
0–30
Bits
0
1
8
9
31
W
R
EIVPR5: 0x5_00A0, EIVPR6: 0x5_00C0, EIVPR7: 0x5_00E0, EIVPR8: 0x5_0100, EIVPR9: 0x5_0120,
EIVPR10: 0x5_0140, EIVPR11: 0x5_0160
MSK
10-36.
1
0
Name
Name
MSK
P0
—
—
A
P
S
A
describes the bits of the MSIDRn.
1
0
describes the EIVPR fields.
Interrupt Source Configuration Registers
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Figure 10-36. External Interrupt Vector/Priority Registers (EIVPR0
External Interrupt Vector/Priority Registers (EIVPR0–EIVPR11)
Reserved.
Processor 0. Set to 1 directs the interrupt to processor 0.
Mask. Masks interrupts from this source.
0 If the corresponding IPR bit is set an interrupt request is generated.
1 Interrupts from this source are disabled.
Activity. A read-only field indicating that an interrupt has been requested or is in-service. Note: The P
(polarity), S (sense), VECTOR and PRIORITY values should not be changed while the corresponding
interrupt is active, that is, while EIVPR n [A] is set.
0 No current interrupt activity associated with this source.
1 The interrupt bit for this source is set in the IPR or ISR.
Reserved.
Polarity. Specifies the polarity for the external interrupt.
0 Polarity is active-low or negative edge triggered.
1 Polarity is active-high or positive edge-triggered.
Sense. Specifies the sense for external interrupts.
0 The external interrupt is edge sensitive.
1 The external interrupt is level-sensitive.
0
2
0 0
—
0
0 0 0 0 0 0 0 0 0 0 0
Table 10-39. MSIDR n Field Descriptions
Table 10-40. EIVPR n Field Descriptions
7
P S
8
9
10 11 12
—
PRIORITY
Description
Description
15 16
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
Programmable Interrupt Controller
VECTOR
–
EIVPR11)
Access: Mixed
10-39
31
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