MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 365

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 9-37
9.5
The DDR SDRAM controller controls processor and I/O interactions with system memory. It provides
support for JEDEC-compliant DDR2 and DDR SDRAMs. The memory system allows a wide range of
memory devices to be mapped to any arbitrary chip select, and support is provided for registered DIMMs
and unbuffered DIMMs. However, registered DIMMs cannot be mixed with unbuffered DIMMs.
Figure 9-33
internal mastering device and the address is decoded to generate the physical bank, logical bank, row, and
column addresses. The transaction is compared with values in the row open table to determine if the
address maps to an open page. If the transaction does not map to an open page, an active command is
issued.
The memory interface supports as many as four physical banks of 64-/72-bit wide or 32-/40bit wide
memory. Bank sizes up to 4 Gbytes are supported, providing up to a maximum of 16 Gbytes of DDR main
memory.
Programmable parameters allow for a variety of memory organizations and timings. Optional error
checking and correcting (ECC) protection is provided for the DDR SDRAM data bus. Using ECC, the
DDR memory controller detects and corrects all single-bit errors within the 64- or 32-bit data bus, detects
all double-bit errors within the 64- or 32-bit data bus, and detects all errors within a nibble. The controller
allows as many as 32 pages to be open simultaneously. The amount of time (in clock cycles) the pages
remain open is programmable with DDR_SDRAM_INTERVAL[BSTOPRE].
Freescale Semiconductor
16–23
24–31
8–15
Bits
0–7
Name
SBEC Single-bit error counter. Indicates the number of single-bit errors detected and corrected since the last error
SBET Single-bit error threshold. Establishes the number of single-bit errors that must be detected before an error
Functional Description
—
—
describes the ERR_SBE fields.
is a high-level block diagram of the DDR memory controller. Requests are received from the
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved
condition is reported.
Reserved
report. If single-bit error reporting is enabled, an error is reported and a machine check or critical interrupt is
generated when this value equals SBET. SBEC is automatically cleared when the threshold value is reached.
Table 9-37. ERR_SBE Field Descriptions
Description
DDR Memory Controller
9-41