MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 608
![BOARD DEVELOPMENT SYSTEM 8544](/photos/37/58/375876/mpc8544e_sml.jpg)
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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- Download datasheet (12Mb)
DUART
Table 13-12
13.3.1.7
The ULCRs specify the data format for the UART bus and set the divisor latch access bit ULCR[DLAB],
which controls the ability to access the divisor latch least and most significant bit registers and the alternate
function register.
After initializing the ULCR, the software should not re-write the ULCR when valid transfers on the UART
bus are active. The software should not re-write the ULCR until the last STOP bit has been received and
there are no new characters being transferred on the bus.
The stick parity bit, ULCR[SP], assigns a set parity value for the parity bit time slot sent on the UART bus.
The set value is defined as mark parity (logic 1) or space parity (logic 0). ULCR[PEN] and ULCR[EPS]
help determine the set parity value. See
number of STOP bits to be sent at the end of the data transfer. The receiver only checks the first STOP bit,
regardless of the number of STOP bits selected. The word length select bits (1 and 0) define the number
of data bits that are transmitted or received as a serial character. The word length does not include START,
parity, and STOP bits.
13-12
Bits
0–1
2–3
4
5
6
7
Name
DMS
RFR
TFR
FEN
RTL
—
describes the fields of the UFCRs.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Receiver trigger level. A received data available interrupt occurs when UIER[ERDAI] is set and the number
of bytes in the receiver FIFO equals the designated interrupt trigger level as follows:
00 1 byte
01 4 bytes
10 8 bytes
11 14 bytes
Reserved
DMA mode select. See
0 UDSR[RXRDY] and UDSR[TXRDY] bits are in mode 0.
1 UDSR[RXRDY] and UDSR[TXRDY] bits are in mode 1 if UFCR[FEN] = 1.
Transmitter FIFO reset
0 No action
1 Clears all bytes in the transmitter FIFO and resets the FIFO counter/pointer to 0
Receiver FIFO reset
0 No action
1 Clears all bytes in the receiver FIFO and resets the FIFO counter/pointer to 0
FIFO enable
0 FIFOs are disabled and cleared
1 Enables the transmitter and receiver FIFOs
Line Control Registers (ULCR0, ULCR1)
Table 13-12. UFCR Field Descriptions
Section 13.4.5.2, “DMA Mode Select,”
Table 13-14
for more information. ULCR[NSTB], defines the
Description
for more information.
Freescale Semiconductor
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