MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 211

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 5-10
The appropriate L1 MMU (instruction or data) is checked for a matching address translation. The
instruction L1 MMU and data L1 MMU operate independently and can be accessed in parallel, so that hits
for instruction accesses and data accesses can occur in the same clock. If an L1 MMU misses, the request
for translation is forwarded to the unified (instruction and data) L2 MMU. If found, the contents of the
TLB entry are concatenated with the byte address to obtain the physical address of the requested access.
On misses, the L1 TLB entries are replaced from their L2 TLB counterparts using a true LRU algorithm.
5.9.2
MMU assist registers are used to hold values either read from or to be written to the TLBs and information
required to identify the TLB to be accessed. MAS3 implements the real page number (RPN), the user
attribute bits (U0–U3), and permission bits (UX, SX, UW, SW, UR, SR) that specify user and supervisor
read, write, and execute permissions.
The e500 does not implement MAS5.
Freescale Semiconductor
Instruction Access
512-Entry 4-Way Set Assoc. Array (TLB0)
* Number of bits depends on page size
16-Entry Fully-Assoc. VSP Array (TLB1)
shows the same translation flow for the e500v2 core.
MMU Assist Registers (MAS0–MAS4 and MAS6–MAS7)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
(4 Kbytes–4 Gbytes)
•••
Figure 5-10. Effective-to-Real Address Translation Flow (e500v2)
L2 MMU (unified)
IS DS •••
36-bit Real Address
Data Access
AS
MSR
8 bits
PID0
PID2
PID1
4–24 bits*
0–20 bits*
Three 41-bit Virtual Addresses (VAs)
Instruction L1 MMU
Real Page Number
Effective Page Number
2 TLBs
L1 MMUs
32-bit Effective Address (EA)
Data L1 MMU
2 TLBs
12–32 bits*
12–32 bits*
Byte Address
Byte Address
Core Complex Overview
5-25