MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 881

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In the case of an individual address, the DA field of the received frame is compared with the physical
address that the user programs in the station address registers (MACSTNADDR1 and MACSTNADDR2).
If the DA does not match the station address, and exact MAC address matching is enabled via
RCTRL[EMEN], the controller performs address recognition on the multiple MAC addresses written to
the MACxADDR1 and MACxADDR2 registers. These virtual addresses give a particular eTSEC the
ability to mirror other MACs on the network, which caters for router redundancy protocols, such as HSRP
and VRRP.
If exact MAC address matching is not enabled, the eTSEC determines whether DA is a group or individual
address. If DA is the standard broadcast address, and broadcast addresses are not rejected, the frame is
accepted. If any other group address is received, the eTSEC looks-up the DA by means of the group hash
table. The group hash table may be extended to 512 entries if RCTRL[GHTX] = 1. Otherwise, an
individual address is hashed into the 256-entry individual hash table when RCTRL[GHTX] = 0.
15.6.3.7.2
The hash table process used in the group hash filtering operates as follows. By default, the Ethernet
controller maps any 48-bit destination address into one of 256 bins, represented by the 256 bits in
IGADDR0–IGADDR7 for individual addresses, and the 256 bits in GADDR0–GADDR7 for group
addresses. But in the case where RCTRL[GHTX] is set, both sets of registers are combined into an
extended group-only hash table of 512 bits, where IGADDR0–IGADDR7 contain the first 256 bits and
GADDR0–GADDR7 contain the last 256 bits. No individual-address table exists in extended mode.
The 48-bit destination address received by the MAC is passed through the Ethernet CRC-32 algorithm to
produce a hash value. The CRC polynomial used is:
The MAC initializes its CRC register to 0xFFFFFFFF before computing a CRC on the 6 bit-reversed octets
of the DA. A non-optimized sample of C code for computing the DA hash is listed in
9 most significant bits of the raw, uninverted CRC are used as the hash table index, H[8:0]. If
RCTRL[GHTX] = 0, bits H[8:6] select one of the 8 IGADDR or GADDR registers, while bits H[5:1]
select a bit within the 32-bit register. If RCTRL[GHTX] = 1, bits H[8:5] select one of the 16 registers in
the {IGADDR, GADDR} set, while bits H[4:0] select a bit within the 32-bit register. For example, if
H[8:5] = 7, IGADDR7 is selected, whereas H[8:5] = 9 selects GADDR1.
Freescale Semiconductor
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MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Hash Table Algorithm
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Enhanced Three-Speed Ethernet Controllers
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