MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 83

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table
Number
18-17
18-18
18-19
18-20
18-21
18-22
18-23
18-24
18-25
18-26
18-27
18-28
18-29
18-30
18-31
18-32
18-33
18-34
18-35
18-36
18-37
18-38
18-39
18-40
18-41
18-42
18-43
18-44
18-45
18-46
18-47
18-48
Freescale Semiconductor
PCI Express Outbound Window Base Address Register n Field Descriptions................... 18-22
PEXOWARn Field Descriptions ......................................................................................... 18-22
PCI Express Inbound Translation Address Registers Field Descriptions ........................... 18-26
PCI Express Inbound Window Base Address Register Field Descriptions ........................ 18-26
PCI Express Inbound Window Base Extended Address
PCI Express Inbound Window Attributes Registers Field Descriptions............................. 18-27
PCI Express Error Detect Register Field Descriptions ....................................................... 18-30
PCI Express Error Interrupt Enable Register Field Descriptions ....................................... 18-32
PCI Express Error Disable Register Field Descriptions ..................................................... 18-34
PCI Express Error Capture Status Register Field Descriptions .......................................... 18-36
PCI Express Error Capture Register 0 Field Descriptions
PCI Express Error Capture Register 0 Field Descriptions
PCI Express Error Capture Register 1 Field Descriptions
PCI Express Error Capture Register 1 Field Descriptions
PCI Express Error Capture Register 2 Field Descriptions
PCI Express Error Capture Register 2 Field Descriptions
PCI Express Error Capture Register 3 Field Descriptions
PEX Error Capture Register 3 Field Descriptions
PCI Express Vendor ID Register Field Description............................................................ 18-44
PCI Express Device ID Register Field Description ............................................................ 18-44
PCI Express Command Register Field Descriptions .......................................................... 18-45
PCI Express Status Register Field Descriptions ................................................................. 18-46
PCI Express Revision ID Register Field Descriptions........................................................ 18-47
PCI Express Class Code Register Field Descriptions ......................................................... 18-48
PCI Express Bus Cache Line Size Register Field Descriptions.......................................... 18-48
PCI Express Bus Latency Timer Register Field Descriptions ............................................ 18-49
PCI Express Bus Latency Timer Register Field Descriptions ............................................ 18-49
PEXCSRBAR Field Descriptions ....................................................................................... 18-51
32-Bit Memory Base Address Register (BAR1) Field Descriptions .................................. 18-51
64-Bit Low Memory Base Address Register Field Descriptions........................................ 18-52
Bit Setting for 64-Bit High Memory Base Address Register.............................................. 18-52
PCI Express Subsystem Vendor ID Register Field Description ......................................... 18-53
Register Field Descriptions ............................................................................................ 18-27
Internal Source, Outbound Transaction.......................................................................... 18-37
External Source, Inbound Transaction ........................................................................... 18-37
Internal Source, Outbound Transaction.......................................................................... 18-38
External Source, Inbound Transaction ........................................................................... 18-39
Internal Source, Outbound Transaction.......................................................................... 18-40
External Source, Inbound Transaction ........................................................................... 18-40
Internal Source, Outbound Transaction.......................................................................... 18-41
External Source, Inbound Transaction ........................................................................... 18-41
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
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