MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 730
![BOARD DEVELOPMENT SYSTEM 8544](/photos/37/58/375876/mpc8544e_sml.jpg)
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
- Current page: 730 of 1340
- Download datasheet (12Mb)
Local Bus Controller
Synchronous Burst Write
Figure 14-89
The DSI samples HA, HDST, HCID, HD, HWBE, HRDE, and HBRST on the first HCLKIN rising edge
on which HCS is asserted. If HCID[0:3] match the CHIPID value, the DSI is accessed. HWBE are
asserted, HBRST is asserted, and HRDE is negated. Assertion of HTA indicates that the DSI is ready to
complete the current beat of the access and the host must proceed to the next beat of this access. When the
host reaches the last beat of the access, it must terminate the burst access. Typically HTA is asserted
immediately for each beat of the access. If the write buffer is full, HTA assertion is delayed. Because HTA
is connected to the LUPWAIT signal of the UPM, all local bus signals are frozen until HTA goes to 0 and
then the UPM continues in its pattern. After the last beat of the access, HTA is driven to logic 1 and stops
being driven on the next rising edge of HCLKIN. The host can start its next access to the same MSC8102
immediately in the next HCLKIN rising edge without negating HCS between accesses. If the next access
is not to the same MSC8102, then, to prevent contention on HTA, the host must wait to access the next
device until the previous DSI stops driving HTA. The easiest way to achieve this is to insert idle cycles at
the end of the UPM pattern to guarantee that HTA is inactive.
14-110
HWBE[0:7]
Legend:
HDST[0:1]
Timing conventions:
HA[11:29]
HCID[0:3]
1
0
1
0
HD[0:63]
HCLKIN
HBRST
HRDE
HCS
shows a synchronous burst write access.
HTA
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Valid value that can be 1 or 0
Don’t care
Three-state output signal that is not driven by the DSI
Figure 14-89. Synchronous Burst Write to MSC8102 DSI
D(A)
A
D(A+1)
D(A+2)
n = 3 in 64-bit data bus interface
n = 7 in 32-bit data bus interface
D(A+2)
D(A+ n )
Freescale Semiconductor
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