MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 715
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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- Download datasheet (12Mb)
To improve the timing margins a PLL is used to generate external clocks, which minimize the skew
between the local bus and the memory clock.
PLL.
14.5.4.4
Contrary to older DRAM technologies, SDRAM devices typically are organized either x4, x8, x16, or x32.
There are no mainstream devices that include parity support. To allow for error protection on the local bus
an additional SDRAM for the 4 parity bits must be used. Since the local bus allows for SDRAM accesses
with less than the full port size, read-modify-write cycles are supported for SDRAM write cycles.
Freescale Semiconductor
LBC output signals on pins
RBC (reference bus clock)
LSYNC_IN
LSYNC_OUT
LCLK
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Parity Support for SDRAM
Figure 14-77. Local Bus PLL Operation
t
D
= t
PLL
Figure 14-77
+t
P
t
P
t
L
shows relative timings for the local bus clock
Local Bus Controller
14-95
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