MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 763

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 15-9
Freescale Semiconductor
10–12
16–27
Bits
0–1
4–6
13
14
15
28
29
2
3
7
8
9
EBERRDIS Ethernet controller bus error disable.
XFUNDIS
BABTDIS
BSYDIS
TXEDIS
CRLDIS
FIRDIS
FIQDIS
LCDIS
Name
describes the fields of the EDIS register.
—
—
—
—
—
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved
Busy disable.
0 Allow eTSEC to report IEVENT[BSY] status and halt buffer descriptor queue if BSY condition occurs.
1 Do not set IEVENT[BSY] and do not halt buffer descriptor queue if BSY condition occurs.
0 Allow eTSEC to report IEVENT[EBERR] status and halt buffer descriptor queue if EBERR condition
1 Do not set IEVENT[EBERR] and do not halt buffer descriptor queue if EBERR condition occurs.
Reserved
Babbling transmit error disable.
0 Allow eTSEC to report IEVENT[BABT] status and set the buffer descriptor TR field.
1 Do not set IEVENT[BABT] nor the buffer descriptor TR field.
Reserved
Transmit error disable.
0 Allow eTSEC to report IEVENT[TXE] status.
1 Do not set IEVENT[TXE] if TXE condition occurs.
Reserved
Late collision disable.
0 Allow eTSEC to report IEVENT[LC] status, set the buffer descriptor LC field, and halt buffer descriptor
1 Do not set IEVENT[LC] nor the buffer descriptor LC field, and do not halt buffer descriptor queue if
Collision retry limit disable.
0 Allow eTSEC to report IEVENT[CRL] status, set the buffer descriptor RL field, and halt buffer
1 Do not set IEVENT[CRL] nor the buffer descriptor RL field, and do not halt buffer descriptor queue if
Transmit FIFO underrun disable.
0 Allow eTSEC to report IEVENT[XFUN] status, set the buffer descriptor UN field, and halt buffer
1 Do not set IEVENT[XFUN] nor the buffer descriptor UN field, and do not halt buffer descriptor queue
Reserved
Filer invalid result error disable.
0 Allow eTSEC to report IEVENT[FIR] status.
1 Do not set IEVENT[FIR] if eTSEC fails to reach a definite filer result when attempting to file a received
Filed frame to invalid queue error disable.
0 Allow eTSEC to report IEVENT[FIQ] status.
1 Do not set IEVENT[FIQ] if eTSEC attempts to file a received frame to an invalid (disabled) RxBD ring,
occurs.
queue if LC condition occurs.
LC condition occurs.
descriptor queue if CRL condition occurs.
CRL condition occurs.
descriptor queue if XFUN condition occurs.
if XFUN condition occurs.
frame, but discard the frame silently.
but discard the frame silently.
Table 15-9. EDIS Field Descriptions
Description
Enhanced Three-Speed Ethernet Controllers
15-31