MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 82
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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- Download datasheet (12Mb)
Table
Number
17-31
17-32
17-33
17-34
17-35
17-36
17-37
17-38
17-39
17-40
17-41
17-42
17-43
17-44
17-45
17-46
17-47
17-48
17-49
17-50
17-51
17-52
17-53
17-54
18-1
18-2
18-3
18-4
18-5
18-6
18-7
18-8
18-9
18-10
18-11
18-12
18-13
18-14
18-15
18-16
lxxxii
PCI Bus Base Class Code Register Field Description ........................................................ 17-35
PCI Bus Cache Line Size Register Field Descriptions ....................................................... 17-36
PCI Bus Latency Timer Register Field Descriptions .......................................................... 17-36
PCSRBAR Field Descriptions ............................................................................................ 17-37
32-Bit Memory Base Address Register Field Descriptions ................................................ 17-37
64-Bit Low Memory Base Address Register Field Descriptions........................................ 17-38
Bit Setting for 64-Bit High Memory Base Address Register.............................................. 17-38
PCI Subsystem Vendor ID Register Field Description ....................................................... 17-38
PCI Subsystem ID Register Field Description.................................................................... 17-39
PCI Bus Capabilities Pointer Register Field Description ................................................... 17-39
PCI Bus Interrupt Line Register Field Description............................................................. 17-40
PCI Bus Interrupt Pin Register Field Description............................................................... 17-40
PCI Bus Minimum Grant Register Field Description ......................................................... 17-40
PCI Bus Maximum Latency Register Field Description .................................................... 17-41
PCI Bus Function Register Field Descriptions ................................................................... 17-41
PCI Bus Arbiter Configuration Register Field Descriptions .............................................. 17-42
PCI Bus Commands ............................................................................................................ 17-46
Supported Combinations of PCI_AD[1:0].......................................................................... 17-48
PCI Configuration Space Header Summary ....................................................................... 17-59
PCI Type 0 Configuration—Device Number to ADn Translation...................................... 17-62
Special-Cycle Message Encodings ..................................................................................... 17-64
PCI Mode Error Actions ..................................................................................................... 17-66
Affected Configuration Register Bits for POR ................................................................... 17-67
Power-On Reset Values for Affected Configuration Bits ................................................... 17-68
POR Parameters for PCI Express Controller ........................................................................ 18-4
PCI Express Interface Signals—Detailed Signal Descriptions............................................. 18-5
PCI Express Memory-Mapped Register Map ....................................................................... 18-6
PEX_CONFIG_ADDR Field Descriptions ........................................................................ 18-10
PEX_CONFIG_DATA Field Descriptions ......................................................................... 18-10
PEX_OTB_CPL_TOR Field Descriptions ......................................................................... 18-11
PEX_CONF_RTY_TOR Field Descriptions ...................................................................... 18-12
PEX_CONFIG Field Descriptions...................................................................................... 18-12
PEX_PME_MES_DR Field Descriptions........................................................................... 18-13
PEX_PME_MES_DISR Field Descriptions ....................................................................... 18-15
PEX_PME_MES_IER Field Descriptions.......................................................................... 18-16
PEX_PMCR Field Descriptions.......................................................................................... 18-18
PCI Express IP Block Revision Register 1 Field Descriptions........................................... 18-18
PCI Express IP Block Revision Register 2 Field Descriptions........................................... 18-19
PEXOTARn Field Descriptions .......................................................................................... 18-20
PCI Express Outbound Extended Address Translation
Register n Field Descriptions ......................................................................................... 18-21
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
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