MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 714

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Local Bus Controller
Setup and Hold Timing Calculations:
Address TOF (time of flight): board layout delay
Data TOF (time of flight): board layout delay
Clock skew (time of flight): clock skew between the LBC and the clock at the memory device. The local
bus PLL feedback mechanism must be used to control this skew to optimize the timing margins, as
described in the rest of this subsection.
Address setup margin = cycle time – local bus address CTQ – SDRAM address input setup time – address
TOF + clock skew
Address hold margin = local bus address output hold time + address TOF – SDRAM address input hold
time – clock skew
Data write to SDRAM setup margin = cycle time – local bus data CTQ – SDRAM data input setup time –
data TOF + clock skew
Data write to SDRAM hold margin = local bus data output hold time + data TOF – SDRAM data input
hold time – clock skew
Data read from SDRAM setup margin = cycle time – SDRAM data CTQ – local bus data input setup time
– data TOF – clock skew
Data read from SDRAM hold margin = SDRAM data output hold time + data TOF – local bus data input
hold time + clock skew
14-94
Note:AC characteristics compiled from worst-case numbers from various data sheets from Samsung and
CLK cycle time
CLK to valid output delay
Output data hold time
Input setup time
Input hold time
CLK to output in Hi-Z
Micron.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Parameter
Table 14-43. SDRAM AC Characteristics
CAS latency = 3
CAS latency = 2
CAS latency = 3
CAS latency = 2
CAS latency = 3
CAS latency = 2
CAS latency = 3
CAS latency = 2
Min
2.5
1.5
—
—
—
—
—
—
6
1
166 MHz
1000
Max
Device Speed
—
—
—
—
—
—
5
5
Min
7.5
7.5
5.4
5.4
—
—
3
3
2
1
133 MHz
1000
Max
Freescale Semiconductor
5.4
5.4
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns