MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 692
![BOARD DEVELOPMENT SYSTEM 8544](/photos/37/58/375876/mpc8544e_sml.jpg)
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
- Current page: 692 of 1340
- Download datasheet (12Mb)
Local Bus Controller
previous RAM word. When LUPWAIT is negated, the UPM continues normal functions. Note that during
WAIT cycles, the UPM does not handle data.
Figure 14-62
to hold the UPM in a particular state until LUPWAIT is negated. As the example shows, the LCSn and
LGPL1 states and the WAEN value are frozen until LUPWAIT is recognized as negated. WAEN is
typically set before the line that contains UTA = 1. Note that if WAEN and NA are both set in the same
RAM word, NA causes the burst address to increment once as normal regardless of whether the UPM
freezes.
14.4.4.5
If LUPWAIT is to be considered an asynchronous signal, which can be asserted/negated at any time, no
UPM RAM word must contain both WAEN = 1 and UTA = 1 simultaneously.
However, programming WAEN = 1 and UTA = 1 in the same RAM word allows UPM to treat LUPWAIT
as a synchronous signal, which must meet set-up and hold times in relation to the rising edge of the bus
clock. In this case, as soon as UPM samples LUPWAIT negated on the rising edge of the bus clock, it
immediately generates an internal transfer acknowledge, which allows a data transfer one bus clock cycle
later. The generation of transfer acknowledge is early because LUPWAIT is not re-synchronized, and the
acknowledge occurs regardless of whether UPM was already frozen in WAIT cycles or not. This feature
allows the synchronous negation of LUPWAIT to affect a data transfer, even if UTA, WAEN, and LAST
are set simultaneously.
14-72
shows how the WAEN bit in the word read by the UPM and the LUPWAIT signal are used
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
LUPWAIT
Synchronous Sampling of LUPWAIT for Early Transfer Acknowledge
LGPL1
WAEN
LCLK
LCS n
T1
T2
T3
T4
TA
c1 c2 c3 c4 c5 c6 c7 c8
Word n
A
Figure 14-62. Effect of LUPWAIT Signal
Word n+1
B
c9 c10 c11
Word n+2
C
c12
Wait
Freescale Semiconductor
Word n+3
c13 c14
D
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