MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 18

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Paragraph
Number
11.4.1.1
11.4.1.2
11.4.1.3
11.4.1.4
11.4.1.5
11.4.1.5.1
11.4.1.5.2
11.4.1.6
11.4.2
11.4.2.1
11.4.3
11.4.4
11.4.4.1
11.4.4.2
11.4.4.2.1
11.4.4.2.2
11.4.4.3
11.4.5
11.4.5.1
11.4.5.2
11.5
11.5.1
11.5.2
11.5.3
11.5.4
11.5.5
11.5.6
11.5.7
11.5.7.1
11.5.7.2
11.5.8
12.1
12.1.1
12.1.2
12.1.2.1
12.1.2.1.1
12.1.2.1.2
xviii
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Initialization/Application Information ......................................................................... 11-21
SEC 2.1 Architecture Overview .................................................................................... 12-2
Arbitration Procedure .............................................................................................. 11-15
Handshaking ............................................................................................................ 11-16
Clock Control........................................................................................................... 11-16
Boot Sequencer Mode.............................................................................................. 11-17
Initialization Sequence............................................................................................. 11-21
Generation of START .............................................................................................. 11-22
Post-Transfer Software Response ............................................................................ 11-22
Generation of STOP................................................................................................. 11-23
Generation of Repeated START .............................................................................. 11-23
Generation of SCL When SDA Low ....................................................................... 11-23
Slave Mode Interrupt Service Routine..................................................................... 11-23
Interrupt Service Routine Flowchart........................................................................ 11-24
Descriptors ................................................................................................................. 12-4
Execution Units (EUs) ............................................................................................... 12-5
START Condition ................................................................................................ 11-12
Slave Address Transmission................................................................................ 11-12
Repeated START Condition ................................................................................ 11-13
STOP Condition................................................................................................... 11-13
Protocol Implementation Details ......................................................................... 11-14
Address Compare—Implementation Details ....................................................... 11-15
Arbitration Control .............................................................................................. 11-15
Clock Synchronization......................................................................................... 11-16
Input Synchronization and Digital Filter ............................................................. 11-16
Clock Stretching .................................................................................................. 11-17
EEPROM Calling Address .................................................................................. 11-19
EEPROM Data Format ........................................................................................ 11-19
Slave Transmitter and Received Acknowledge ................................................... 11-24
Loss of Arbitration and Forcing of Slave Mode.................................................. 11-24
Public Key Execution Unit (PKEU) ...................................................................... 12-5
Transaction Monitoring—Implementation Details.......................................... 11-14
Control Transfer—Implementation Details ..................................................... 11-14
Input Signal Synchronization .......................................................................... 11-17
Filtering of SCL and SDA Lines ..................................................................... 11-17
Elliptic Curve Operations .................................................................................. 12-5
Modular Exponentiation Operations ................................................................. 12-6
Security Engine (SEC) 2.1
Contents
Chapter 12
Title
Freescale Semiconductor
Number
Page