MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 423

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 10-17
10.3.2.4
The global timer vector/priority registers (GTVPRs) contain the interrupt vector and the interrupt priority
as shown in
Table 10-18
12–15 PRIORITY Priority. Specifies the interrupt priority. The lowest priority is 0 and the highest priority is 15. A priority level of
16–31 VECTOR Vector. The vector value in this field is returned when the interrupt acknowledge (IACK) register is read and
Freescale Semiconductor
1–31 BASE CNT Base count. When CI transitions from 1 to 0, this value is copied into the corresponding current count register
Bits
2–11
Offset 0x4_1120, 0x4_1160, 0x4_11A0, 0x4_11E0
Reset
Bits
0
0
1
W
R
MSK
Name
1
Name
0
MSK
CI
—
A
A
0
1
Figure
describes the GTBCRn fields.
describes the GTVPRn fields.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Global Timer Vector/Priority Registers (GTVPR n )
0
2
Count inhibit. Always set following reset
0 Counting enabled
1 Counting inhibited
and the toggle bit is cleared. If CI is already cleared (counting is in progress), the base count is copied to the
current count register at the next zero crossing of the current count.
Mask. Inhibits interrupts from this source.
0 Interrupt requests are generated when the corresponding IPR bit is set.
1 Further interrupts from this source are disabled.
Activity. This field is read-only.
0 No current interrupt activity associated with this source.
1 An interrupt has been requested by the corresponding source or is currently being serviced. The interrupt
The VECTOR and PRIORITY values should not be changed while the A bit is set.
Reserved
0 disables interrupts from this source.
this interrupt resides in the interrupt request register shown in
0
bit for this source is set in the IPR or ISR.
10-14. They also contain the mask and activity fields.
0
Figure 10-14. Global Timer Vector/Priority Register (GTVPR n )
0
0
—
0
Table 10-17. GTBCR n Field Descriptions
Table 10-18. GTVPR n Field Descriptions
0
0
0
11 12
0
0
PRIORITY
0
0
15 16
0
Description
Description
0
0
0
0
Figure
0
0
10-48.
0
VECTOR
Programmable Interrupt Controller
0
0
0
0
0
Access: Mixed
0
0
0
10-25
31
0